Hardware Manual - RTD Embedded Technologies, Inc.

Mask Register (BA + 0x1Eh, bits 1 and 0 = 10):
For all bits:
0 = bit enabled
1 = bit masked
D7 D6 D5 D4 D3 D2 D1 D0
P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0
In the Advanced Digital Interrupt modes, this register is used to mask out specific bits when monitoring the bit
pattern present at Port 0 for interrupt generation. In normal operation where the Advanced Digital Interrupt
feature is not being used, any bit which is masked by writing a 1 to that bit will not change state, regardless of the
digital data written to Port 0. For example, if you set the state of bit 0 low and then mask this bit, the state will
remain low, regardless of what you output at Port 0 (an output of 1 will not change the bit’s state until the bit is
unmasked).
Compare Register (BA + 0x1Eh, bits 1 and 0 = 11):
D7 D6 D5 D4 D3 D2 D1 D0
P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0
This register is used for the Advanced Digital Interrupt modes. In the match mode where an interrupt is
generated when the Port 0 bits match a loaded value, this register is used to load the bit pattern to be matched
at Port 0. Bits can be selectively masked so that they are ignored when making a match. NOTE: Make sure that
bit 3 at BA + 0x1Eh is set to 1, selecting match mode, BEFORE writing the Compare Register value at this address.
In the event mode where an interrupt is generated when any Port 0 bit changes its current state, the value which
caused the interrupt is latched at this register and can be read from it. Bits can be selectively masked using the
Mask Register so a change of state is ignored on these lines in the event mode.
50 DM6425HR dataModule BDM-610010034 Rev C