Hardware Manual - RTD Embedded Technologies, Inc.

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Table 11 DM6425HR Specifications Characteristic Specification Interface Jumper-selectablebase address, I/O mapped Software programmable interrupts and DMA channel Analog Input Up to 16 differential or 32 single-ended inputs, software selectable Input Impedance, each channel >10 MΩ Gains, software-selectable 1, 2, 4, and 8 Gain Error 0.05 dB, typ.; 0.1 dB, max. Input Ranges, software selectable ±5, ±10, or 0 to +10 V Overvoltage Protection ±12 VDC Common Mode Input Voltage ±10 V, max. Settling Time (gain = 1) 2 μs, max. A/D Converter Type Successive approximation Resolution 12 bits (2.44 mV @ 10 V; 4.88 mV @ 20 V) Linearity ±1 bit, typ. Conversion Speed 2 μs, typ. Module Throughput 500 kHz Channel-Gain Table Size 1024 x 16 bits Pacer Clock & Sample Counter Range (using onboard 8 MHz clock) 9 minutes to 2 μs Sample Counter Maximum Count (1 cycle) 65,536 Digital I/O Number of Lines (32) Port 0: 8 bit programmable lines Port 1: 1 byte programmable line Port 2: 8 bit programmable lines Port 3: 1 byte programmable line Isource Isink Sample Buffer FIFO Size (A/D) FIFO Size (Digital Input Port 0) D/A Converter Analog Outputs Resolution Output Ranges Relative Accuracy Full-Scale Accuracy Non-Linearity Settling Time –12 MA 24 mA 1024 x 16 bits 1024 x 8 bits AD7245 4 channels 12 bits ± 5, 0 to +5, ±10, or 0 to +10 V ±1 bit, max. ±5 bits, max. ±1 bit, max. 5 μs, max. 120 DM6425HR dataModule BDM-610010034 Rev C
Table 11 DM6425HR Specifications (cont’d) Characteristic Specification Timer/Counters CMOS 82C54 Six 16-bit down counters Six programmable operating modes Counter Input Source External clock (8 MHz, max.) or onboard 8 MHz clock Counter Outputs Available externally; used as PC interrupts Counter Gate Source External gate or always enabled Miscellaneous Inputs/Outputs (PC bus-sourced) ±5 V, ±12 V, ground Power Requirements +5 V, 4.0 W, typ. I/O Connectors (CN3/CN4) 50-pin right angle headers Environmental Operating Temperature –40 to +85°C Storage Temperature –55 to +125°C Humidity 0 to 90%, noncondensing Size 3.55" L x 3.775" W x 0.6" H (90mm x 96mm x 16mm) BDM-610010034 Rev C Appendix C: Specifications 121
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DM6425HR 32-Channel, 500 kHz PC/104
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DM6425 32-Channel, 500 kHz PC/104 d
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Table of Contents Chapter 1 Introdu
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A/D Conversion Modes . . . . . . .
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D/A Calibration. . . . . . . . . .
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Chapter 1 Introduction The DM6425HR
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DM6425HR Ordering Information The D
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Features The DM6425HR is a 12-bit,
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Analog-to-Digital Conversion The DM
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8254 Timer/Counters Two 8254 progra
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For More Information This manual an
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Chapter 2 DM6425HR Module Settings
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JS1 JS2 JS3 JS4 Figure 6 DM6425HR S
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Base Address Jumper (Factory Settin
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Chapter 3 Installing the dataModule
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Installation Considerations Conside
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External I/O Connections Figure 13
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Connecting the Analog Input Pins Th
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I/O CONNECTOR (CN3) SIGNAL SOURCE 1
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Chapter 4 I/O Mapping This chapter
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BDM-610010034 Rev C Chapter 4: I/O
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Load Channel-Gain Table in Channel-
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This register sets up the trigger m
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BA + 0x0Ah (10): Digital Input FIFO
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BA + 0x18h (24): Digital I/O Port 0
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BA + 0x1Eh (30): Digital IRQ Status
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BA + 0x408h (1032): DAC3 Update Reg
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BA + 0x41Ch (1052): Read/Program Po
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BA + 0x800h/801h (2048/2049): Board
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Setting or clearing more than one b
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Chapter 5 A/D Conversions This chap
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Programming Channel, Gain, Input Ra
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Pause Bit Bit 11 is used as a pause
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With BA + 0x00h, bits 1 and 0 set t
Page 79 and 80: TO A/D CONVERTER A/D CONVERSION SEL
Page 81 and 82: Trigger Repeat Function Bit 13 in t
Page 83 and 84: Programmable Burst In this mode, a
Page 85 and 86: Voltage values for each bit will va
Page 87 and 88: Programming Steps The pacer clock i
Page 89 and 90: Using the Sample Counter to Create
Page 91 and 92: Mathematical formula for calculatin
Page 93 and 94: Chapter 6 Data Transfers Using DMA
Page 95 and 96: Allocating a DMA Buffer When using
Page 97 and 98: Setting the DMA Page Register Oddly
Page 99 and 100: Programming the DM6425HR for DMA On
Page 101 and 102: Chapter 7 Interrupts This chapter e
Page 103 and 104: CLOCK DIGITAL INPUT IRQ OUT Figure
Page 105 and 106: If you find yourself intimidated by
Page 107 and 108: Restoring the Startup IMR and Inter
Page 109 and 110: Chapter 8 D/A Conversions This chap
Page 111 and 112: Chapter 9 Timer/Counters This chapt
Page 113 and 114: Each timer/counter has two inputs,
Page 115 and 116: Chapter 10 Digital I/O This chapter
Page 117 and 118: When using event interrupts, you ca
Page 119 and 120: Appendix A Example Programs This ap
Page 121 and 122: Special Considerations When manipul
Page 123 and 124: Appendix B Calibration This appendi
Page 125 and 126: A/D Calibration Two procedures are
Page 127 and 128: Below is a table listing the ideal
Page 129: Appendix C Specifications This appe
Page 133 and 134: Appendix D I/O Connector Pin Assign
Page 135 and 136: Mating Connector Part Numbers Manuf
Page 137 and 138: Appendix E IDAN Dimensions and Pino
Page 139 and 140: IDAN-DM6425HR-62S External I/O Conn
Page 141 and 142: IDAN-DM6425HR-68S External I/O Conn
Page 143 and 144: Appendix F Limited Warranty RTD Emb
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