Hardware Manual - RTD Embedded Technologies, Inc.

The DM6425HR has two completely independent interrupt circuits that can generate interrupts on IRQ
channels 3, 5, 9, 10, 11, 12, or 15. By using these two circuits, complex data acquisition systems can be configured.
Software Selectable Interrupt Sources
Each interrupt circuit on the DM6425HR has 16 software selectable interrupt sources that can be programmed
in bits 0 through 4 and bits 8 through 12 of the Interrupt Register at BA + 0x08h, as described and shown below.
Software Selectable Interrupt Channel
Each interrupt circuit on the DM6425HR has 7 software selectable interrupt channels that can be programmed
in bits 5 through 7 and bits 13 through 15 of the Interrupt Register at BA + 0x08h. The interrupt output is driven
by an open collector device which is turned off when the IRQ channel is set to disable. At power up or reset, this
register is set to all zeroes.
Advanced Digital Interrupts
The bit programmable digital I/O circuitry supports two Advanced Digital Interrupt modes, event mode or
match mode. These modes are used to monitor input lines for state changes. The mode is selected at
BA + 0x1Eh, bit 3 and enabled at BA + 0x1Eh, bit 4.
Event Mode
When enabled, this mode samples the Port 0 input lines at a specified clock rate (using the 8 MHz system clock
or a programmable clock in User TC Counter 1), looking for a change in state in any one of the eight bits. When
a change of state occurs, an interrupt is generated and the input pattern is latched into the Compare Register.
You can read the contents of this register at BA + 0x1Ch to see which bit caused the interrupt to occur. Bits can
be masked and their state changes ignored by programming the Mask Register with the mask at BA + 0x1Ch.
Match Mode
When enabled, this mode samples the Port 0 input lines at a specified clock rate (using the 8 MHz system clock
or a programmable clock in User TC Counter 1) and compares all input states to the value programmed in the
Compare Register at BA + 0x1Ch. When the states of all of the lines match the value in the Compare Register, an
interrupt is generated. Bits can be masked and their states ignored by programming the Mask Register with the
mask at BA + 0x1Ch.
Sampling Digital Lines for Change of State
In the Advanced Digital Interrupt modes, the digital lines are sampled at a rate set by the 8 MHz system clock or
the clock programmed in User TC Counter 1. With each clock pulse, the digital circuitry looks at the state of the
next Port 0 bits. To provide noise rejection and prevent erroneous interrupt generation because of noise spikes
on the digital lines, a change in the state of any bit must be seen for two edges of a clock pulse to be recognized
by the circuit. Figure 30 shows a diagram of this circuit.
92 DM6425HR dataModule BDM-610010034 Rev C