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The Noninverting CFA + V IN G = 1 + Z B – IZ I G = 1 V OUT Z G V A Z F Figure 8–4. Noninverting CFA Equation 8–6 is the transfer equation, Equation 8–7 is the current equation at the inverting node, and Equation 8–8 is the input loop equation. These equations are combined to yield the closed-loop gain equation, Equation 8–9. V OUT IZ I V A Z G – V OUT –V A Z F (8–6) (8–7) V A V IN –IZ B (8–8) Z1 Z F Z G Z F 1 Z B V Z F Z G (8–9) OUT V IN 1 Z Z F 1 Z B Z F Z G When the input buffer output impedance, Z B , approaches zero, Equation 8–9 reduces to Equation 8–10. 8-4
The Inverting CFA V OUT V IN Z1 Z F Z G Z F 1 Z Z F 1 Z F Z G 1 Z F Z (8–10) When the transimpedance, Z, is very high, the term Z F /Z in Equation 8–10 approaches zero, and Equation 8–10 reduces to Equation 8–11; the ideal closed-loop gain equation for the CFA. The ideal closed-loop gain equations for the CFA and VFA are identical, and the degree to which they depart from ideal is dependent on the validity of the assumptions. The VFA has one assumption that the direct gain is very high, while the CFA has two assumptions, that the transimpedance is very high and that the input buffer output impedance is very low. As would be expected, two assumptions are much harder to meet than one, thus the CFA departs from the ideal more than the VFA does. V OUT V IN 1 Z F Z G (8–11) 8.5 The Inverting CFA The inverting CFA configuration is seldom used because the inverting input impedance is very low (Z B ||Z F +Z G ). When Z G is made dominant by selecting it as a high resistance value it overrides the effect of Z B . Z F must also be selected as a high value to achieve at least unity gain, and high values for Z F result in poor bandwidth performance, as we will see in the next section. If Z G is selected as a low value the frequency sensitive Z B causes the gain to increase as frequency increases. These limitations restrict inverting applications of the inverting CFA. + G = 1 + Z B IZ – I V IN Z G V A Z F G = 1 V OUT Figure 8–5. Inverting CFA Current-Feedback Op Amp Analysis 8-5
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Design Reference August 2002 Advanc
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Forward Everyone interested in anal
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Contents Contents 1 The Op Amp’s
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Contents 10 Op Amp Noise Theory and
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Contents 14.4.3 AC Application Erro
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Contents 17.7.1 Through-Hole Consid
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Figures Figures 2-1 Ohm’s Law App
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Figures 7-5 TL08X Frequency and Tim
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Figures 13-12 Differential Amplifie
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Figures 16-41 Comparison of Q Betwe
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Figures A-37 Basic Wien Bridge Osci
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Examples Examples 16-1 First-Order
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Chapter 1 The Op Amp’s Place In T
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The first signal conditioning op am
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Chapter 2 Review of Circuit Theory
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Voltage Divider Rule source, throug
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Thevenin’s Theorem 2.5 Thevenin
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Thevenin’s Theorem V OUT V TH R
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Calculation of a Saturated Transist
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Transistor Amplifier 2 V (from 8 V
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Chapter 3 Development of the Ideal
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The Noninverting Op Amp 3.2 The Non
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The Adder 3-5, and if R F = 100 k a
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Complex Feedback Networks portion o
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Video Amplifiers 3.7 Video Amplifie
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Summary 3.9 Summary When the proper
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Chapter 4 Single-Supply Op Amp Desi
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Circuit Analysis R G R F +V V IN _
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Circuit Analysis V OUT VCC -V IN
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Circuit Analysis R G R F V CC V REF
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Simultaneous Equations m 2 1 0.1
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Simultaneous Equations R F R G R G
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Simultaneous Equations measured 4.5
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Simultaneous Equations +5V R 2 820
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Simultaneous Equations |m| 5.56 R
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Simultaneous Equations 4.3.4 Case 4
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Simultaneous Equations -0.10 -0.15
Page 75 and 76: Chapter 5 Feedback and Stability Th
Page 77 and 78: Block Diagram Math and Manipulation
Page 79 and 80: Block Diagram Math and Manipulation
Page 81 and 82: Bode Analysis of Feedback Circuits
Page 87 and 88: Loop Gain Plots are the Key to Unde
Page 89 and 90: The Second Order Equation and Ringi
Page 91 and 92: Chapter 6 Development of the Non Id
Page 93 and 94: Review of the Canonical Equations T
Page 95 and 96: Noninverting Op Amps 6.3 Noninverti
Page 97 and 98: Inverting Op Amps The transfer equa
Page 99 and 100: Differential Op Amps A aZ G Z G Z
Page 101 and 102: Chapter 7 Voltage-Feedback Op Amp C
Page 103 and 104: Internal Compensation Figure 7-2 sh
Page 105 and 106: Internal Compensation AVD - Large-S
Page 107 and 108: Internal Compensation - Large-Signa
Page 109 and 110: Dominant-Pole Compensation 7.4 Domi
Page 111 and 112: Dominant-Pole Compensation 100 dB D
Page 113 and 114: Lead Compensation Gain compensation
Page 115 and 116: Lead Compensation slopes down at -2
Page 117 and 118: Compensated Attenuator Applied to O
Page 119 and 120: Lead-Lag Compensation C R + _ V OUT
Page 121 and 122: Conclusions Dominant pole compensat
Page 123 and 124: Chapter 8 Current-Feedback Op Amp A
Page 125: The Noninverting CFA output impedan
Page 129 and 130: Stability Analysis 8.6 Stability An
Page 131 and 132: Selection of the Feedback Resistor
Page 133 and 134: Stability and Input Capacitance Tab
Page 135 and 136: Compensation of CF and CG Z F A R
Page 137 and 138: Chapter 9 Voltage- and Current-Feed
Page 139 and 140: Bandwidth The noninverting input of
Page 141 and 142: Bandwidth The CFA is a current oper
Page 143 and 144: Impedance The CFA stability is not
Page 145 and 146: Equation Comparison Table 9-1. Tabu
Page 147 and 148: Chapter 10 Op Amp Noise Theory and
Page 149 and 150: Characterization 10.2.2 Noise Floor
Page 151 and 152: Types of Noise 10.3.1 Shot Noise Th
Page 153 and 154: Types of Noise as average dc curren
Page 155 and 156: Types of Noise Some characteristics
Page 157 and 158: Noise Colors There are an infinite
Page 159 and 160: Op Amp Noise 1000 Hz V n - Input No
Page 161 and 162: Op Amp Noise can be represented bet
Page 163 and 164: Op Amp Noise This simplifies the ga
Page 165 and 166: Putting It All Together 10.6 Puttin
Page 167 and 168: Putting It All Together When it is
Page 169 and 170: References +5 V 100 k +5 V 100 k V
Page 171 and 172: Chapter 11 Understanding Op Amp Par
Page 173 and 174: Operational Amplifier Parameter Glo
Page 175 and 176: Operational Amplifier Parameter Glo
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Operational Amplifier Parameter Glo
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Additional Parameter Information 10
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Additional Parameter Information +V
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Additional Parameter Information of
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Chapter 12 Instrumentation: Sensors
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The system definition specifies the
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pends heavily on test conditions su
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the bias resistor, R 1 , is selecte
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V OUT I D R F (12-6) The phototran
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the semiconductor in a direction pe
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eference has a temperature drift of
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impedance of the transducer. The te
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Y mX b (12-14) Two pairs of data
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Table 12-5. Offset and Gain Error B
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R G 23.7 kΩ R FB 280 kΩ R FA 200
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12.10 Test The final circuit is rea
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Chapter 13 Wireless Communication:
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Wireless Systems ality. Image rejec
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Wireless Systems of the DAC, is usu
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Selection of ADCs/DACs The mean squ
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Selection of ADCs/DACs fication. Wi
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Anti-Aliasing Filters The op amp dy
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Communication D/A Converter Reconst
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External Vref Circuits for ADCs/DAC
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External Vref Circuits for ADCs/DAC
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High-Speed Analog Input Drive Circu
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High-Speed Analog Input Drive Circu
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Chapter 14 Interfacing D/A Converte
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Understanding the D/A Converter and
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Understanding the D/A Converter and
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D/A Converter Error Budget 14.4.1 A
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D/A Converter Error Budget 20 Ampli
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D/A Converter Errors and Parameters
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Increasing Op Amp Buffer Amplifier
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Chapter 15 Sine Wave Oscillators Ro
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Phase Shift in the Oscillator 15.3
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Active Element (Op Amp) Impact on t
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Analysis of the Oscillator Operatio
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Sine Wave Oscillator Circuits Phase
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Sine Wave Oscillator Circuits large
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Sine Wave Oscillator Circuits The i
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Sine Wave Oscillator Circuits R F 1
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Sine Wave Oscillator Circuits V OUT
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Sine Wave Oscillator Circuits resis
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Sine Wave Oscillator Circuits 15.7.
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Chapter 16 Active Filter Design Tec
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Fundamentals of Low-Pass Filters V
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Fundamentals of Low-Pass Filters A(
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Fundamentals of Low-Pass Filters 16
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Fundamentals of Low-Pass Filters 10
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Low-Pass Filter Design The multipli
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Low-Pass Filter Design C 1 R 1 R 2
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Low-Pass Filter Design V IN R 1 R 2
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Low-Pass Filter Design The general
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Low-Pass Filter Design In order to
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High-Pass Filter Design With C 1 =
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High-Pass Filter Design 16.4.1 Firs
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High-Pass Filter Design To simplify
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Band-Pass Filter Design R 1 1 1 2
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Band-Pass Filter Design 16.5.1 Seco
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Band-Pass Filter Design Because of
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Band-Pass Filter Design A mi is
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Band-Pass Filter Design In accordan
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Band-Rejection Filter Design |A| [d
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Band-Rejection Filter Design or to
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All-Pass Filter Design 0 |A| — Ga
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All-Pass Filter Design Inserting th
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All-Pass Filter Design The transfer
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Practical Design Hints 16.8 Practic
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Practical Design Hints +V CC +V CC
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Practical Design Hints The differen
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Practical Design Hints 16.8.4 Op Am
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Filter Coefficient Tables 16.9 Filt
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Filter Coefficient Tables Table 16-
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References 16.10 References D.Johns
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Chapter 17 Circuit Board Layout Tec
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PCB Mechanical Construction 17.2 PC
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PCB Mechanical Construction V+ IN -
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Grounding ponents and feed-throughs
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Grounding components carefully if t
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The Frequency Characteristics of Pa
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Decoupling + Figure 17-15. Logic Ga
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Input and Output Isolation A decoup
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Packages SINGLE DUAL SHORT TRACES L
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Packages and other passive componen
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References 17.8.4 Routing 17.
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Chapter 18 Designing Low-Voltage Op
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Dynamic Range The trick to designin
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Signal-to-Noise Ratio Table 18-1. C
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Input Common-Mode Range Many low vo
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Input Common-Mode Range The input s
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Output Voltage Swing Op amps always
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Single-Supply Circuit Design every
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Transducer to ADC Analog Interface
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DAC to Actuator Analog Interface is
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DAC to Actuator Analog Interface Th
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Comparison of Op Amps Table 18-2. O
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Summary mon-mode range of the op am
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Appendix A Single-Supply Circuit Co
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Introduction + 5 V R G R F +V CC _
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Amplifiers A.3 Amplifiers Many type
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Amplifiers A.3.3 Inverting Op Amp w
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Amplifiers A.3.5 Noninverting Op Am
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Amplifiers A.3.7 Noninverting Op Am
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Amplifiers A.3.9 Differential Ampli
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Amplifiers A.3.11 High Input Impeda
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Amplifiers A.3.13 High-Precision Di
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Amplifiers A.3.15 Variable Gain Dif
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Amplifiers A.3.17 Buffer The buffer
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Amplifiers A.3.19 Noninverting AC A
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Computing Circuits A.4.2 Noninverti
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Computing Circuits A.4.4 Inverting
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Computing Circuits A.4.10 Noninvert
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Oscillators A.5 Oscillators This se
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Oscillators A.5.3 Wien Bridge Oscil
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Oscillators A.5.5 Classical Phase S
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Oscillators A.5.7 Bubba Oscillator
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Appendix BA Single-Supply Op Amp Se
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Table B-1. Single-Supply Operationa
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A AC loads, DAC, 14-2 AC parameters
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low pass filter, 16-1 low-pass filt
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esistor ladder, 14-2 to 14-4 resist
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phase shift for TL07x, 7-5 phase sh
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N Noise, 10-8 to 10-10 avalanche, 1
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packages, 17-24 to 17-27 parallel s
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Theorem Norton’s, 2-5 Superpositi
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