Xilinx PG054 7 Series FPGAs Integrated Block for PCI Express ...

Chapter 2Product SpecificationThe Xilinx® 7 Series FPGAs Integrated Block for PCI Express® contains full support for2.5 Gb/s and 5.0 Gb/s PCI Express Endpoint and Root Port configurations. For 8.0 Gb/s(Gen3) support, see Virtex-7 FPGA Gen3 Integrated Block for PCI Express Product Guide[Ref 3], for device support and information on the Virtex®-7 FPGA Gen3 Integrated Blockfor PCI Express.Table 2-1 defines the Integrated Block for PCIe® solutions.Table 2-1:Product OverviewThe LogiCORE IP 7 Series FPGAs Integrated Block for PCI Express core internallyinstantiates the 7 Series FPGAs Integrated Block for PCI Express (PCIE_2_1). The integratedblock follows the PCI Express Base Specification layering model, which consists of thePhysical, Data Link, and Transaction layers. The integrated block is compliant with thePCI Express Base Specification, rev. 2.1 [Ref 2].Figure 2-1 illustrates these interfaces to the 7 Series FPGAs Integrated Block for PCI Expresscore:• System (SYS) interfaceProduct Name User Interface Width Supported Lane Widths1-lane at 2.5 Gb/s, 5.0 Gb/s 64 x12-lane at 2.5 Gb/s, 5.0 Gb/s 64 x1, x2 (1)4-lane at 2.5 Gb/s, 5.0 Gb/s 64, 128 x1, x2, x4 (1),(2)8-lane at 2.5 Gb/s, 5.0 Gb/s 64, 128 x1, x2, x4, x8 (1),(3)Notes:1. See Link Training: 2-Lane, 4-Lane, and 8-Lane Components, page 146 for additional information.2. The x4 at 2.5 Gb/s option in the CORE Generator tool provides only the 64-bit width interface.3. x8 at 5.0 Gb/s only available in the 128-bit width.• PCI Express (PCI_EXP) interface• Configuration (CFG) interface• Transaction interface (AXI4-Stream)• Physical Layer Control and Status (PL) interface7 Series Integrated Block for PCIe (v1.6) www.xilinx.com 11PG054 July 25, 2012Product Specification