Xilinx PG054 7 Series FPGAs Integrated Block for PCI Express ...

IP FactsIntroductionThe LogiCORE IP 7 Series FPGAs IntegratedBlock for PCI Express® core is a scalable,high-bandwidth, and reliable serial interconnectbuilding block for use with Xilinx® 7 series FPGAfamilies. The Integrated Block for PCI Express(PCIe®) solution supports 1-lane, 2-lane, 4-lane,and 8-lane Endpoint and Root Port configurationsat up to 5 Gb/s (Gen2) speeds, all of which arecompliant with the PCI Express Base Specification,rev. 2.1. This solution supports the AMBA®AXI4-Stream interface for the customer userinterface.With higher bandwidth per pin, low overhead, lowlatency, reduced signal integrity issues, and CDRarchitecture, the Integrated Block for PCIe setsthe industry standard for a high-performance,cost-efficient, third-generation I/O solution.The Integrated Block for PCI Express solution iscompatible with industry-standard applicationform factors such as the PCI Express CardElectromechanical (CEM) v2.0 and the PCIIndustrial Computer Manufacturers Group (PICMG)3.4 specifications.Features• High-performance, highly flexible, scalable,and reliable, general-purpose I/O core° Compliant with the PCI Express BaseSpecification, rev. 2.1° Compatible with conventional PCIsoftware model• Incorporates Xilinx Smart-IP technology toguarantee critical timing• Uses GTXE2 or GTPE2 transceivers for 7 seriesFPGA families° 2.5 GT/s and 5.0 GT/s line speeds° Supports 1-lane, 2-lane, 4-lane, and8-lane operation° Elastic buffers and clock compensation° Automatic clock data recoverySupportedDeviceFamily (1)LogiCORE IP Facts TableCore SpecificsVirtex®-7, Kintex-7, Artix-7SupportedUser InterfacesAXI4-StreamResources See Table 2-2.Design FilesExampleDesignTest BenchConstraintsFileSimulationModelSupportedS/W DriverDesign EntrySimulationSynthesisNotes:Provided with CoreISE: Verilog/VHDL (2) RTL Source and SimulationModelsVivado: Encrypted RTLTested Design Flows (3)Verilog, VHDLVerilog, VHDLISE: UCFVivado: XDCVerilog, VHDLN/AISE® Design Suite v14.2Vivado Design Suite v2012.2 (4)Cadence Incisive Enterprise Simulator (IES)Synopsys VCS and VCS MXMentor Graphics ModelSimXilinx ISimVivado SimulatorSupportXilinx Synthesis Technology (XST)Vivado SynthesisProvided by Xilinx @ www.xilinx.com/support1. For a complete listing of supported devices, see the releasenotes for this core.2. RTL source for the GTX wrapper is Verilog only. VHDL projectsrequire mixed language mode simulators.3. For the supported versions of the tools, see the Xilinx DesignTools: Release Notes Guide.4. Supports only 7 series devices.7 Series Integrated Block for PCIe (v1.6) www.xilinx.com 7PG054 July 25, 2012Product Specification