Xilinx PG054 7 Series FPGAs Integrated Block for PCI Express ...

Core InterfacesCore InterfacesThe 7 Series FPGAs Integrated Block for PCI Express core includes top-level signal interfacesthat have sub-groups for the receive direction, transmit direction, and signals common toboth directions.System InterfaceThe System (SYS) interface consists of the system reset signal (sys_reset) and the systemclock signal (sys_clk), as described in Table 2-5.Table 2-5: System Interface SignalsFunction Signal Name Direction DescriptionSystem Reset sys_reset Input Asynchronous signal. sys_reset must beasserted for at least 1500 ns during poweron and warm reset operations.System Clock sys_clk Input Reference clock: Selectable frequency100 MHz, 125 MHz, or 250 MHz.Some 7 series devices do not have 3.3 V I/Os available. Therefore the appropriate level shiftis required to operate with these devices that contain only 1.8 V banks.The system reset signal is an asynchronous input. The assertion of sys_reset causes ahard reset of the entire core. The reset provided by the PCI Express system is typically activeLow (for example, PERST#) and needs to be inverted before connecting to the sys_resetsignal. The system reset signal is a 3.3 V signal.The system input clock must be 100 MHz, 125 MHz, or 250 MHz, as selected in theCORE Generator tool GUI Clock and Reference signals.PCI Express InterfaceThe PCI Express (PCI_EXP) interface consists of differential transmit and receive pairsorganized in multiple lanes. A PCI Express lane consists of a pair of transmit differentialsignals (pci_exp_txp, pci_exp_txn) and a pair of receive differential signals{pci_exp_rxp, pci_exp_rxn}. The 1-lane core supports only Lane 0, the 2-lane coresupports lanes 0-1, the 4-lane core supports lanes 0-3, and the 8-lane core supports lanes0-7. Transmit and receive signals of the PCI_EXP interface are defined in Table 2-6.7 Series Integrated Block for PCIe (v1.6) www.xilinx.com 15PG054 July 25, 2012Product Specification