Xilinx PG054 7 Series FPGAs Integrated Block for PCI Express ...

General Design GuidelinesX-Ref Target - Figure 3-2AXI Bit 63 32 31 0AXI Byte+7 +6 +5 +4 +3+2 +1 +0PCIe Byte+4 +5 +6 +7 +0 +1+2+37 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0Clock 0Clock 1Requester ID TagLast DWBE1st DWR Fmt TType R TC R EBE x 0D P Attr RData[31:0] Address [31:2] RLengthFigure 3-2:Endpoint Integrated Block Byte OrderPackets sent to the core for transmission must follow the formatting rules for TransactionLayer Packets (TLPs) as specified in the “Transaction Layer Specification” chapter of the PCIExpress Base Specification. The User Application is responsible for ensuring its packets’validity. The core does not check that a packet is correctly formed and this can result intransferring a malformed TLP. The exact fields of a given TLP vary depending on the type ofpacket being transmitted.Transmitting Outbound PacketsBasic TLP Transmit OperationThe 7 Series FPGAs Integrated Block for PCI Express core automatically transmits thesetypes of packets:• Completions to a remote device in response to Configuration Space requests.• Error-message responses to inbound requests that are malformed or unrecognized bythe core.Note: Certain unrecognized requests, for example, unexpected completions, can only bedetected by the User Application, which is responsible for generating the appropriate response.The User Application is responsible for constructing these types of outbound packets:• Memory, Atomic Ops, and I/O Requests to remote devices.• Completions in response to requests to the User Application, for example, a MemoryRead Request.• Completions in response to user-implemented Configuration Space requests, whenenabled. These requests include PCI legacy capability registers beyond address BFhand PCI Express extended capability registers beyond address 1FFh.Note: For important information about accessing user-implemented Configuration Space whilein a low-power state, see Power Management, page 139.When configured as an Endpoint, the 7 Series FPGAs Integrated Block for PCI Express corenotifies the User Application of pending internally generated TLPs that arbitrate for thetransmit datapath by asserting tx_cfg_req (1b). The User Application can choose to givepriority to core-generated TLPs by asserting tx_cfg_gnt (1b) permanently, withoutregard to tx_cfg_req. Doing so prevents User-Application-generated TLPs from being7 Series Integrated Block for PCIe (v1.6) www.xilinx.com 51PG054 July 25, 2012