Xilinx PG054 7 Series FPGAs Integrated Block for PCI Express ...

Transaction InterfaceTable 2-14:Configuration Interface Signals (Cont’d)Name Direction Descriptioncfg_trn_pending Input User Transaction Pending: If asserted, sets theTransactions Pending bit in the Device Status Register.Note: The user is required to assert this input if the UserApplication has not received a completion to anupstream request.cfg_dsn[63:0] Input Configuration Device Serial Number: Serial NumberRegister fields of the Device Serial Number extendedcapability.cfg_pmcsr_pme_en Output PMCSR PME Enable: PME_En bit (bit 8) in the PowerManagement Control/Status Register.cfg_pmcsr_pme_status Output PMCSR PME_Status: PME_Status bit (bit 15) in the PowerManagement Control/Status Register.cfg_pmcsr_powerstate[1:0] Output PMCSR PowerState: PowerState bits (bits 1:0) in thePower Management Control/Status Register.cfg_pm_halt_aspm_l0s Input Halt ASPM L0s: When asserted, it prevents the core fromgoing into ASPM L0s. If the core is already in L0s, itcauses the core to return to L0. cfg_pm_force_state,however, takes precedence over this input.cfg_pm_halt_aspm_l1 Input Halt ASPM L1: When asserted, it prevents the core fromgoing into ASPM L1 (1) . If the core is already in L1, itcauses the core to return to L0. cfg_pm_force_state,however, takes precedence over this input.cfg_pm_force_state[1:0] Input Force PM State: Forces the Power Management Statemachine to attempt to stay in or move to the desiredstate.• 00: Move to or stay in L0• 01: Move to or stay in PPM L1• 10: Move to or stay in ASPM L0s• 11: Move to or stay in ASPM L1 (1)cfg_pm_force_state_en Input Force PM State Transition Enable: Enables the transitionto/stay in the desired Power Management state, asindicated by cfg_pm_force_state. If attempting tomove to a desired state, cfg_pm_force_state_enmust be held asserted until cfg_pcie_link_stateindicates a move to the desired state.cfg_received_func_lvl_rst Output Received Function Level Reset: Indicates when theFunction Level Reset has been received (FLRConfiguration Register has been set).cfg_vc_tcvc_map[6:0] Output Configuration VC Resource Control TC/VC Map:Indicates whether TCs 1 through 7 are valid for VC0.cfg_msg_received Output Message Received: Active High. Notifies the user that aMessage TLP was received on the Link.7 Series Integrated Block for PCIe (v1.6) www.xilinx.com 31PG054 July 25, 2012Product Specification