Xilinx PG054 7 Series FPGAs Integrated Block for PCI Express ...

More documents

Recommendations

Info

Standards ComplianceThe core uses packets to exchange information between the various modules. Packets areformed in the Transaction and Data Link Layers to carry information from the transmittingcomponent to the receiving component. Necessary information is added to the packetbeing transmitted, which is required to handle the packet at those layers. At the receivingend, each layer of the receiving element processes the incoming packet, strips the relevantinformation and forwards the packet to the next layer.As a result, the received packets are transformed from their Physical Layer representation totheir Data Link Layer representation and the Transaction Layer representation.X-Ref Target - Figure 2-1LogiCORE IP 7 Series FPGAsIntegrated Block for PCI ExpressTXBlock RAMRXBlock RAMUserLogicAXI4-StreamInterfacePhysical LayerControl and StatusHostInterfacePhysical(PL)Configuration(CFG)7 Series FPGAsIntegrated Block forPCI Express(PCIE_2_1)TransceiversPCI Express(PCI_EXP)Optional DebugPCIExpressFabricUser LogicUserLogicOptional Debug(DRP)System(SYS)ClockandResetFigure 2-1:Top-Level Functional Blocks and InterfacesStandards ComplianceThe 7 Series FPGAs Integrated Block for PCI Express is compliant with the PCI Express BaseSpecification, rev. 2.1 [Ref 2].Resource UtilizationTable 2-2 shows the resources for the 7 series FPGAs Integrated Block for PCI Express corefor ISE® Design Suite implementations.7 Series Integrated Block for PCIe (v1.6) www.xilinx.com 12PG054 July 25, 2012Product Specification
Minimum Device RequirementsTable 2-2:Resources UsedProductInterfaceWidthGTXE1 LUT (1) FF (1) RX BuffersSize (KB)TX BuffersSize (KB)CMPS (2)(Bytes)BlockRAMMMCMsClockBuffers1-lane Gen1/Gen2 (3) 64-bit 1 400 5752-lane Gen1/Gen264-bit 2 525 7504-lane Gen1 64-bit 4 800 11004-lane Gen264-bit,128-bit4 800 13008 or 16 4-32 128-1024 2-16 1 58-lane, Gen164-bit,128-bit8 1350 22758-lane, Gen2 128-bit 8 1450 2600Notes:1. Numbers are for the default core configuration. Actual LUT and FF utilization values vary based on specific configurations.2. Capability Maximum Payload Size (CMPS).3. Gen1 speeds are 2.5 Gb/s. Gen2 speeds are 5.0 Gb/s.Minimum Device RequirementsTable 2-3 lists the minimum device requirements for 7 series FPGAs Integrated Block for PCIExpress configurations.Table 2-3:7 Series FPGAs Integrated Block for PCI Express ConfigurationsArtix-7FPGAs (1) Kintex-7 FPGAs Virtex-7 FPGAsXC7A100TXC7A200TXC7A350TXC7K480TXC7K420XC7K410TXC7K355TXC7K325TXCK7160T (2)XC7K70T (2) XC7VX485T XC7V585T XC7V1500T (3) XC7V2000T (3)Number of Integrated Blocks forPCIe (see Table 2-4)1 1 4 3 3 4Gen1 (2.5 Gb/s) 1–4 1–8 1–8 1–8 1–8 1–8LanesGen2 (5.0 Gb/s) 1–4 1–8 1–8 1–8 1–8 1–8Gen3 (8.0 Gb/s) (4) — — — — — —x1–x4 Gen1-1, -2, -3,-2L-1, -2, -3, -2L -1, -2, -3, -2L -1, -2, -3, -2L -1, -2, -2L -1, -2, -2LSpeed Gradex8 Gen1 NA -1, -2, -3, -2L -1, -2, -3, -2L -1, -2, -3, -2L -1, -2, -2L -1, -2, -2Lx1–x4 Gen2 -2, -3 -1, -2, -3, -2L -1, -2, -3, -2L -1, -2, -3, -2L -1, -2, -2L -1, -2, -2Lx8 Gen2 NA -2, -3, -2L (1V) -2, -3, -2L (1V) -2, -3, -2L (1V) -2, -2L (1V) -2, -2L (1V)7 Series Integrated Block for PCIe (v1.6) www.xilinx.com 13PG054 July 25, 2012Product Specification
Page 1 and 2: 7 Series FPGAsIntegrated Block forP
Page 3: Chapter 5: Constraining the CoreReq
Page 6 and 7: SECTION I: SUMMARYIP FactsOverviewP
Page 8 and 9: Features (Continued)• Supports En
Page 10 and 11: Applications• Flow-control manage
Page 14 and 15: Available Integrated Blocks for PCI
Page 16 and 17: Core InterfacesTable 2-6:LaneNumber
Page 18 and 19: Transaction InterfaceTransaction In
Page 20 and 21: Transaction InterfaceTable 2-9: Tra
Page 22 and 23: Transaction InterfaceTable 2-10: Re
Page 24 and 25: Transaction InterfaceTable 2-10: Re
Page 26 and 27: Transaction InterfaceTable 2-11:Phy
Page 28 and 29: Transaction InterfaceTable 2-11:Phy
Page 30 and 31: Transaction InterfaceTable 2-14:Con
Page 34 and 35: Transaction InterfaceTable 2-16:Rol
Page 38 and 39: Transaction InterfaceTable 2-18: Us
Page 40 and 41: Transaction InterfaceTable 2-19:Err
Page 42 and 43: Transaction InterfaceTable 2-20:Dyn
Page 44 and 45: PCI Configuration SpaceThe core imp
Page 46 and 47: PCI Configuration SpaceTable 2-22:C
Page 48 and 49: PCI Configuration SpaceTable 2-23:T
Page 50 and 51: .General Design GuidelinesDesigning
Page 52 and 53: General Design Guidelinestransmitte
Page 54 and 55: General Design GuidelinesX-Ref Targ
Page 60 and 61: General Design Guideliness_axis_tx_
Page 62 and 63:
General Design GuidelinesX-Ref Targ
Page 64 and 65:
Page 66 and 67:
General Design Guidelines• Receiv
Page 68 and 69:
Page 70 and 71:
General Design GuidelinesDesigning
Page 72 and 73:
General Design Guidelinesis asserti
Page 74 and 75:
Page 76 and 77:
Page 78 and 79:
Page 80 and 81:
Page 82 and 83:
General Design GuidelinesTable 3-4:
Page 84 and 85:
Page 86 and 87:
Page 88 and 89:
General Design GuidelinesPacket Re-
Page 90 and 91:
General Design GuidelinesUser Appli
Page 92 and 93:
Page 94 and 95:
Page 96 and 97:
General Design GuidelinesTable 3-10
Page 98 and 99:
General Design GuidelinesFor exampl
Page 100 and 101:
General Design Guidelines• fc_ph[
Page 102 and 103:
General Design GuidelinesIn the cas
Page 104 and 105:
General Design Guidelines• Before
Page 106 and 107:
General Design GuidelinesDirected L
Page 108 and 109:
Page 110 and 111:
General Design GuidelinesDevice Con
Page 112 and 113:
General Design Guidelinescfg_lstatu
Page 114 and 115:
Page 116 and 117:
Page 118 and 119:
General Design Guidelines3. Vendor
Page 120 and 121:
General Design GuidelinesUser logic
Page 122 and 123:
Page 124 and 125:
Page 126 and 127:
General Design GuidelinesHandling M
Page 128 and 129:
Page 130 and 131:
Page 132 and 133:
Page 134 and 135:
Page 136 and 137:
Page 138 and 139:
Page 140 and 141:
General Design GuidelinesActive Sta
Page 142 and 143:
General Design GuidelinesPower-down
Page 144 and 145:
General Design GuidelinesLegacy Int
Page 146 and 147:
General Design GuidelinesIf Per-Vec
Page 148 and 149:
General Design GuidelinesUsing the
Page 150 and 151:
Page 152 and 153:
Page 154 and 155:
Page 156 and 157:
Page 158 and 159:
Page 160 and 161:
General Design GuidelinesDesign Flo
Page 162 and 163:
Page 164 and 165:
General Design GuidelinesVC707:CONF
Page 166 and 167:
General Design Guidelinesdesign use
Page 168 and 169:
General Design GuidelinesThese inpu
Page 170 and 171:
General Design Guidelinesdesign-dep
Page 172 and 173:
General Design Guidelinescommunicat
Page 174 and 175:
Page 176 and 177:
Page 178 and 179:
General Design GuidelinesAREA_GROUP
Page 180 and 181:
General Design GuidelinesThe Persis
Page 182 and 183:
General Design Guidelines3. When th
Page 184 and 185:
General Design GuidelinesPower-supp
Page 186 and 187:
ClockingWith these items implemente
Page 188 and 189:
ClockingX-Ref Target - Figure 3-89P
Page 190 and 191:
Protocol LayersProtocol LayersThe f
Page 192 and 193:
FPGA ConfigurationThis section disc
Page 194 and 195:
FPGA ConfigurationX-Ref Target - Fi
Page 196 and 197:
FPGA Configuration100 ms ≤ T PWRV
Page 198 and 199:
FPGA ConfigurationX-Ref Target - Fi
Page 200 and 201:
SECTION II: VIVADO DESIGN SUITECust
Page 202 and 203:
GUIX-Ref Target - Figure 4-1Figure
Page 204 and 205:
GUISelecting the alternate frequenc
Page 206 and 207:
GUI• Type: BARs can either be I/O
Page 208 and 209:
GUIID Initial Values• Vendor ID:
Page 210 and 211:
Page 212 and 213:
GUI• Extended Tag Field: Indicate
Page 214 and 215:
GUI• Hardware Autonomous Speed Di
Page 216 and 217:
Page 218 and 219:
Page 220 and 221:
Page 222 and 223:
Page 224 and 225:
GUIPinout SelectionThe Pinout Selec
Page 226 and 227:
GUIX-Ref Target - Figure 4-13Transa
Page 228 and 229:
GUI• Force No Scrambling: Used fo
Page 230 and 231:
Output Generation/< component_name_
Page 232 and 233:
Device, Package, and Speed Grade Se
Page 234 and 235:
Core Timing ConstraintsPhysical con
Page 236 and 237:
Supported Core PinoutsTable 5-2:Pac
Page 238 and 239:
Chapter 6Getting Started Example De
Page 240 and 241:
Directory and File ContentsTable 6-
Page 242 and 243:
Example DesignTable 6-5:sample_test
Page 244 and 245:
Example DesignX-Ref Target - Figure
Page 246 and 247:
Generating the Core1. Start the Viv
Page 248 and 249:
Generating the CoreX-Ref Target - F
Page 250 and 251:
Generating the CoreX-Ref Target - F
Page 252 and 253:
SimulationX-Ref Target - Figure 6-1
Page 254 and 255:
Chapter 7Example Design and Model T
Page 256 and 257:
Programmed Input/Output: Endpoint E
Page 258 and 259:
Page 260 and 261:
Page 262 and 263:
Page 264 and 265:
Page 266 and 267:
Page 268 and 269:
Page 270 and 271:
Root Port Model Test Bench for Endp
Page 272 and 273:
Page 274 and 275:
Page 276 and 277:
Page 278 and 279:
Page 280 and 281:
Page 282 and 283:
Page 284 and 285:
Page 286 and 287:
Configurator Example Design• Conf
Page 288 and 289:
Configurator Example DesignThe Conf
Page 290 and 291:
Configurator Example Designconfigur
Page 292 and 293:
Endpoint Model Test Bench for Root
Page 294 and 295:
SECTION III: ISE DESIGN SUITECustom
Page 296 and 297:
Page 298 and 299:
GUISelecting the alternate frequenc
Page 300 and 301:
GUI• Checkbox: Click the checkbox
Page 302 and 303:
Page 304 and 305:
Page 306 and 307:
GUI• Extended Tag Field: Indicate
Page 308 and 309:
GUI• De-emphasis: Sets the level
Page 310 and 311:
GUIPower Management RegistersThe Po
Page 312 and 313:
Page 314 and 315:
Page 316 and 317:
Page 318 and 319:
GUIX-Ref Target - Figure 9-12Transa
Page 320 and 321:
Output Generation• Disable TX ASP
Page 322 and 323:
Device, Package, and Speed Grade Se
Page 324 and 325:
Core Timing Constraintsphysical con
Page 326 and 327:
Supported Core PinoutsTable 10-2:Pa
Page 328 and 329:
Supported Core PinoutsTable 10-2:Su
Page 330 and 331:
Directory and File Contentssimulati
Page 332 and 333:
Directory and File Contentsimplemen
Page 334 and 335:
Directory and File ContentsTable 11
Page 336 and 337:
Example DesignX-Ref Target - Figure
Page 338 and 339:
Generating the CoreFor help startin
Page 340 and 341:
Generating the Core6. In the Compon
Page 342 and 343:
Simulation• routed.v[hd]Verilog o
Page 344 and 345:
Chapter 12Example Design and Model
Page 346 and 347:
Page 348 and 349:
Page 350 and 351:
Page 352 and 353:
Page 354 and 355:
Page 356 and 357:
Page 358 and 359:
Page 360 and 361:
Page 362 and 363:
Page 364 and 365:
Page 366 and 367:
Page 368 and 369:
Page 370 and 371:
Page 372 and 373:
Page 374 and 375:
Page 376 and 377:
Configurator Example Design• Conf
Page 378 and 379:
Configurator Example DesignThe Conf
Page 380 and 381:
Configurator Example Designconfigur
Page 382 and 383:
Endpoint Model Test Bench for Root
Page 384 and 385:
SECTION IV: APPENDICESMigratingDebu
Page 386 and 387:
Migration ConsiderationsTable A-1:C
Page 388 and 389:
TRN to AXI Migration Considerations
Page 390 and 391:
Page 392 and 393:
Page 394 and 395:
Page 396 and 397:
Page 398 and 399:
Contacting Xilinx Technical Support
Page 400 and 401:
Debug Tools• lspci -x -d []:[]Thi
Page 402 and 403:
Hardware DebugX-Ref Target - Figure
Page 404 and 405:
Hardware DebugFPGA Configuration Ti
Page 406 and 407:
Hardware Debug• A component must
Page 408 and 409:
Hardware Debug• Memory or I/O req
Page 410 and 411:
Hardware Debugthat error detection
Page 412 and 413:
Hardware Debug• Replay NUM Rollov
Page 414 and 415:
Simulation DebugX-Ref Target - Figu
Page 416 and 417:
Simulation Debug# [ 149143316] : TS
Page 418 and 419:
Appendix CManaging Receive-Buffer S
Page 420 and 421:
Methods of Managing Completion Spac
Page 422 and 423:
Page 424 and 425:
Page 426 and 427:
Transaction Layer InterfaceTable D-
Page 428 and 429:
Transaction Layer InterfaceTable D-
Page 430 and 431:
Block RAM InterfaceTable D-2: Trans
Page 432 and 433:
GTX Transceiver InterfaceTable D-4:
Page 434 and 435:
Page 436 and 437:
Page 438 and 439:
Configuration Management InterfaceT
Page 440 and 441:
Page 442 and 443:
Page 444 and 445:
Page 446 and 447:
Page 448 and 449:
Page 450 and 451:
Page 452 and 453:
Page 454 and 455:
Page 456 and 457:
Page 458 and 459:
Page 460 and 461:
Page 462 and 463:
Page 464 and 465:
Page 466 and 467:
Page 468 and 469:
Page 470 and 471:
TL2 Interface PortsTable D-16: Debu
Page 472 and 473:
Appendix EAdditional ResourcesXilin
Page 474:
Revision HistoryRevision HistoryThe
show all

Xilinx PG054 7 Series FPGAs Integrated Block for PCI Express ...

Create successful ePaper yourself

Delete template?

Save as template?