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Xilinx PG054 7 Series FPGAs Integrated Block for PCI Express ...

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Transaction InterfaceTable 2-19:Error-Reporting Interface - Root Port Only (Cont’d)Name Direction Descriptioncfg_aer_rooterr_non_fatal_err_reporting_en Output AER Non-Fatal Error ReportingEnable: Indicates status of the AERNon-Fatal Error Reporting Enable bitin the AER Root Error Commandconfiguration register. This bitenables the user logic to generateInterrupts <strong>for</strong> reported Non-FatalErrors.cfg_aer_rooterr_fatal_err_reporting_en Output AER Fatal Error Reporting Enable:Indicates status of the AER Fatal ErrorReporting Enable bit in the AER RootError Command configurationregister. This bit enables the userlogic to generate Interrupts <strong>for</strong>reported Fatal Errors.cfg_aer_rooterr_corr_err_received Output AER Correctable Error MessageReceived: Indicates status of the AERCorrectable Error Message Receivedbit in the AER Root Error Statusconfiguration register. This bitindicates that a Correctable Errormessage was received.cfg_aer_rooterr_non_fatal_err_received Output AER Non-Fatal Error MessageReceived: Indicates status of the AERNon-Fatal Error Message Receivedbit in the AER Root Error Statusconfiguration register. This bitindicates that a Non-Fatal Errormessage was received.cfg_aer_rooterr_fatal_err_received Output AER Fatal Error Message Received:Indicates status of the AER Fatal ErrorMessage Received bit in the AERRoot Error Status configurationregister. This bit indicates that a FatalError message was received.Dynamic Reconfiguration Port InterfaceThe Dynamic Reconfiguration Port (DRP) interface allows <strong>for</strong> the dynamic change of FPGAconfiguration memory bits of the 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Integrated</strong> <strong>Block</strong> <strong>for</strong> <strong>PCI</strong> <strong>Express</strong> core.These configuration bits are represented as attributes <strong>for</strong> the <strong>PCI</strong>E_2_1 library primitive,which is instantiated as part of this core. Table 2-20 defines the DRP interface signals. Fordetailed usage in<strong>for</strong>mation, see Using the Dynamic Reconfiguration Port Interface,page 148.7 <strong>Series</strong> <strong>Integrated</strong> <strong>Block</strong> <strong>for</strong> <strong>PCI</strong>e (v1.6) www.xilinx.com 41<strong>PG054</strong> July 25, 2012Product Specification

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