Xilinx PG054 7 Series FPGAs Integrated Block for PCI Express ...

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Transaction InterfaceTable 2-20:Dynamic Reconfiguration Port Interface SignalsName Direction Descriptionpcie_drp_clk Input PCI Express DRP Clock: The rising edge of this signal is thetiming reference for all the other DRP signals. Normally,drp_clk is driven with a global clock buffer. The maximumfrequency is defined in the appropriate 7 Series FPGAs DataSheet.pcie_drp_en Input PCI Express DRP Data Enable: When asserted, this signalenables a read or write operation. If drp_dwe is deasserted,it is a read operation, otherwise a write operation. For anygiven drp_clk cycle, all other input signals are don’t caresif drp_den is not active.pcie_drp_we Input PCI Express DRP Write Enable: When asserted, this signalenables a write operation to the port (see drp_den).pcie_drp_addr[8:0] Input PCI Express DRP Address Bus: The value on this busspecifies the individual cell that is written or read. Theaddress is presented in the cycle that drp_den is active.pcie_drp_di[15:0] Input PCI Express DRP Data Input: The value on this bus is the datawritten to the addressed cell. The data is presented in thecycle that drp_den and drp_dwe are active, and iscaptured in a register at the end of that cycle, but the actualwrite occurs at an unspecified time before drp_drdy isreturned.pcie_drp_rdy Output PCI Express DRP Ready: This signal is a response to drp_dento indicate that the DRP cycle is complete and another DRPcycle can be initiated. In the case of a DRP read, the drp_dobus must be captured on the rising edge of drp_clk in thecycle that drp_drdy is active. The earliest that drp_den cango active to start the next port cycle is the same clock cyclethat drp_drdy is active.pcie_drp_do[15:0] Output PCI Express DRP Data Out: If drp_dwe was inactive whendrp_den was activated, the value on this bus whendrp_drdy goes active is the data read from the addressedcell. At all other times, the value on drp_do[15:0] isundefined.Clocking Interface for Partial ReconfigurationThe clocking interface provided to the user supports Partial Reconfiguration by use ofclocking external to the PCI Express design. Table 2-21 defines the clocking interfacesignalsTable 2-21: Clocking Interface SignalsName Direction DescriptionPIPE_PCLK_IN Input Parallel clock used to synchronize data transfers acrossthe parallel interface of the GTX transceiver.PIPE_RXUSRCLK_IN Input Provides a clock for the internal RX PCS datapath.7 Series Integrated Block for PCIe (v1.6) www.xilinx.com 42PG054 July 25, 2012Product Specification
PCI Configuration SpaceTable 2-21: Clocking Interface Signals (Cont’d)Name Direction DescriptionPIPE_RXOUTCLK_IN Input Recommended clock output to the FPGA logic.PIPE_DCLK_IN Input Dynamic reconfiguration clock.PIPE_USERCLK1_IN Input Optional user clock.PIPE_USERCLK2_IN Input Optional user clock.PIPE_MMCM_LOCK_IN Input Indicates if the MMCM is locked onto the source CLK.PIPE_TXOUTCLK_OUT Output Recommended clock output to the FPGA logic.PIPE_RXOUTCLK_OUT Output Recommended clock output to the FPGA logic.PIPE_PCLK_SEL_OUT Output Parallel clock select.PIPE_GEN3_OUT Output Indicates the PCI Express operating speed.The Clocking architecture is described in detail in the Use Model chapter of the 7 SeriesFPGAs GTX/GTH Transceivers User Guide [Ref 3].PCI Configuration SpaceThe PCI configuration space consists of three primary parts, illustrated in Table 2-22. Theseinclude:• Legacy PCI v3.0 Type 0/1 Configuration Space Header° Type 0 Configuration Space Header used by Endpoint applications (see Table 2-23)° Type 1 Configuration Space Header used by Root Port applications (see Table 2-24)• Legacy Extended Capability Items° PCIe Capability Item° Power Management Capability Item° Message Signaled Interrupt (MSI) Capability Item° MSI-X Capability Item (optional)• PCIe Extended Capabilities° Device Serial Number Extended Capability Structure (optional)° Virtual Channel Extended Capability Structure (optional)° Vendor Specific Extended Capability Structure (optional)° Advanced Error Reporting Extended Capability Structure (optional)° Resizable BAR Extended Capability Structure (optional)7 Series Integrated Block for PCIe (v1.6) www.xilinx.com 43PG054 July 25, 2012Product Specification
Page 1 and 2: 7 Series FPGAsIntegrated Block forP
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Appendix EAdditional ResourcesXilin
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Revision HistoryRevision HistoryThe
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