Xilinx PG054 7 Series FPGAs Integrated Block for PCI Express ...

Chapter 3Designing with the CoreThis chapter includes guidelines and additional information to make designing with thecore easier. It provides design instructions for the Xilinx® 7 Series FPGAs Integrated Blockfor PCI Express® user interface and assumes knowledge of the PCI Express TransactionLayer Packet (TLP) header fields. Header fields are defined in PCI Express Base Specificationv2.1 [Ref 2], in the “Transaction Layer Specification” chapter.This chapter contains these sections:• General Design Guidelines• Clocking• Resets• Protocol Layers• FPGA ConfigurationGeneral Design GuidelinesThis section provides design guidelines on these topics:• Designing with the Transaction Layer Interface• Designing with the Physical Layer Control and Status Interface• Design with Configuration Space Registers and Configuration Interface• Error Detection• Power Management• Generating Interrupt Requests• Link Training: 2-Lane, 4-Lane, and 8-Lane Components• Lane Reversal• Using the Dynamic Reconfiguration Port Interface• Tandem PROM• Tandem PCIe (ISE Tool Flow)7 Series Integrated Block for PCIe (v1.6) www.xilinx.com 49PG054 July 25, 2012