Xilinx PG054 7 Series FPGAs Integrated Block for PCI Express ...

Chapter 1OverviewXilinx® 7 series FPGAs include three unified FPGA families that are all designed for lowestpower to enable a common design to scale across families for optimal power, performance,and cost. The Artix-7 family is optimized for lowest cost and absolute power for thehighest volume applications. The Virtex®-7 family is optimized for highest systemperformance and capacity. The Kintex-7 family is an innovative class of FPGAs optimizedfor the best price to performance. This document describes the function and operation ofthe 7 Series FPGAs Integrated Block for PCI Express®, including how to design, customize,and implement it.The LogiCORE IP 7 Series FPGAs Integrated Block v1.6 for PCI Express core is a reliable,high-bandwidth, scalable serial interconnect building block. The core instantiates the7 Series FPGA Integrated Block for PCI Express found in the 7 series FPGAs, and supportsboth Verilog-HDL and VHDL. This Integrated Block for PCIe simplifies the design processand reduces time-to-market. It is configurable for Endpoint and Root Port applications. Thissolution can be used in communication, multimedia, server and mobile platforms andenables applications such as high-end medical imaging, graphics intensive video games,DVD quality streaming video on the desktop, and 10 Gigabit Ethernet interface cards.Although the 7 Series FPGAs Integrated Block for PCI Express core is a fully verifiedsolution, the challenge associated with implementing a complete design varies dependingon the configuration and functionality of the application. For best results, previousexperience building high-performance, pipelined FPGA designs using Xilinximplementation software and constraints files is recommended.Feature SummaryThe 7 Series FPGAs Integrated Block for PCI Express follows the PCI Express BaseSpecification, rev. 2.1 [Ref 2] layering model, which consists of the Physical, Data Link, andTransaction Layers. The protocol uses packets to exchange information between layers.Packets are formed in the Transaction and Data Link Layers to carry information from thetransmitting component to the receiving component. Necessary information is added tothe packet being transmitted, which is required to handle the packet at specific layers.The functions of the protocol layers include:• Generating and processing of TLPs7 Series Integrated Block for PCIe (v1.6) www.xilinx.com 9PG054 July 25, 2012