Xilinx PG054 7 Series FPGAs Integrated Block for PCI Express ...

Transaction InterfaceTable 2-15:cfg_pm_wake Input Configuration Power Management Wake: Aone-clock cycle assertion informs the core togenerate and send a Power Management WakeEvent (PM_PME) Message TLP to the upstreamlink partner.Note: The user is required to assert this inputonly under stable link conditions as reportedon the cfg_pcie_link_state[2:0] bus.Assertion of this signal when the PCI Expresslink is in transition results in incorrect behavioron the PCI Express link.cfg_msg_received_pm_as_nak Output Received Power Management Active State NAKMessage: Indicates that a PM_AS_NAKMessage was received on the link.cfg_msg_received_setslotpowerlimit Output Received Set Slot Power Limit: Indicates that aSet Slot Power Limit Message was received onthe link. The data of the Set Slot Power LimitMessage is delivered on the cfg_msg_dataoutput.Table 2-16:Role-Specific Configuration Interface Signals: Endpoint (Cont’d)Name Direction DescriptionRole-Specific Configuration Interface Signals: Root PortName Direction Descriptioncfg_ds_bus_number[7:0] Input Configuration Downstream Bus Number: Provides thebus number (Requester ID) of the Downstream Port. Thisis used in TLPs generated inside the core and does notaffect the TLPs presented on the AXI4-Stream interface.cfg_ds_device_number[4:0] Input Configuration Downstream Device Number: Providesthe device number (Requester ID) of the DownstreamPort. This is used in TLPs generated inside the core anddoes not affect the TLPs presented on the Transactioninterface.cfg_ds_function_number[2:0] Input Configuration Downstream Function Number: Providesthe function number (Requester ID) of the DownstreamPort. This is used in TLPs generated inside the core anddoes not affect the TLPs presented on the Transactioninterface.cfg_wr_rw1c_as_rw Input Configuration Write RW1C Bit as RW: Indicates that thecurrent write operation should treat any RW1C bit as aRW bit. Normally, a RW1C bit is cleared by writing a 1 toit, and can normally only be set by internal coreconditions. However, during a configuration registeraccess operation with this signal asserted, for every biton cfg_di that is 1, the corresponding RW1Cconfiguration register bit is set to 1. A value of 0 oncfg_di during this operation has no effect, andnon-RW1C bits are unaffected regardless of the value oncfg_di.7 Series Integrated Block for PCIe (v1.6) www.xilinx.com 33PG054 July 25, 2012Product Specification