Xilinx PG054 7 Series FPGAs Integrated Block for PCI Express ...

Transaction InterfaceTable 2-12: Role-Specific Physical Layer Interface Signals: EndpointName Direction Descriptionpl_received_hot_rst Output Hot Reset Received: Indicates that an in-band hotreset command has been received.Table 2-13:Role-Specific Physical Layer Interface Signals: Root PortName Direction Descriptionpl_transmit_hot_rst Input Transmit Hot Reset: Active High. Directs the PCIExpress Port to transmit an In-Band Hot Reset.pl_downstream_deemph_source Input Root Port Preferred Transmitter De-emphasis:Enables the Root Port to control de-emphasisused on the link at 5.0 Gb/s speeds.• 0: Use Upstream link partner preferredde-emphasis.• 1: Use Selectable de-emphasis value fromLink Control 2 register.Configuration InterfaceThe Configuration (CFG) interface enables the user design to inspect the state of theEndpoint for PCIe configuration space. The user provides a 10-bit configuration address,which selects one of the 1024 configuration space doubleword (DWORD) registers. TheEndpoint returns the state of the selected register over the 32-bit data output port.Table 2-14 defines the Configuration interface signals. See Design with ConfigurationSpace Registers and Configuration Interface, page 109 for usage.Table 2-14:Configuration Interface SignalsName Direction Descriptioncfg_mgmt_do[31:0] Output Configuration Data Out: A 32-bit data output port usedto obtain read data from the configuration space insidethe core.cfg_mgmt_rd_wr_done Output Configuration Read Write Done: Read-write done signalindicates a successful completion of the userconfiguration register access operation.• For a user configuration register read operation, thissignal validates the cfg_mgmt_do[31:0] data-busvalue.• For a user configuration register write operation, theassertion indicates completion of a successful writeoperation.cfg_mgmt_di[31:0] Input Configuration Data In: A 32-bit data input port used toprovide write data to the configuration space inside thecore.7 Series Integrated Block for PCIe (v1.6) www.xilinx.com 29PG054 July 25, 2012Product Specification