Xilinx PG054 7 Series FPGAs Integrated Block for PCI Express ...

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Transaction InterfaceTable 2-10: Receive Interface Signals (Cont’d)Name Mnemonic Direction Descriptionrx_np_ok Input Receive Non-Posted OK: The User Application assertsthis signal when it is ready to accept Non-PostedRequest TLPs. rx_np_ok must be deasserted whenthe User Application cannot process receivedNon-Posted TLPs, so that these can be buffered withinthe core's receive queue. In this case, Posted andCompletion TLPs received after the Non-Posted TLPsbypass the blocked TLPs.When the User Application approaches a state whereit is unable to service Non-Posted Requests, it mustdeassert rx_np_ok two clock cycle before the coreasserts m_axis_rx_tlast of the next-to-lastNon-Posted TLP the User Application can accept.rx_np_req Input Receive Non-Posted Request: When asserted,requests one non-posted TLP from the core peruser_clk cycle. If the User Application can processreceived Non-Posted TLPs at the line rate, this signalcan be constantly asserted. If the User Application isnot requesting Non-Posted packets, received Postedand Completion TLPs bypass waiting Non-PostedTLPs.m_axis_rx_tuser[9:2] rx_bar_hit[7:0] Output Receive BAR Hit: Indicates BAR(s) targeted by thecurrent receive transaction. Asserted from thebeginning of the packet to m_axis_rx_tlast.• (rx_bar_hit[0])m_axis_rx_tuser[2]: BAR0• (rx_bar_hit[1])m_axis_rx_tuser[3]: BAR1• (rx_bar_hit[2])m_axis_rx_tuser[4]: BAR2• (rx_bar_hit[3])m_axis_rx_tuser[5]: BAR3• (rx_bar_hit[4])m_axis_rx_tuser[6]: BAR4• (rx_bar_hit[5])m_axis_rx_tuser[7]: BAR5• (rx_bar_hit[6])m_axis_rx_tuser[8]:Expansion ROM AddressIf two BARs are configured into a single 64-bitaddress, both corresponding rx_bar_hit bits areasserted.m_axis_rx_tuser[8:4] are not applicable to RootPort configurations.m_axis_rx_tuser[9] is reserved for future use.m_axis_rx_tuser[16:15]Physical Layer InterfaceReservedThe Physical Layer (PL) interface enables the user design to inspect the status of the Linkand Link Partner and control the Link State. Table 2-11 describes the signals for the PLinterface.7 Series Integrated Block for PCIe (v1.6) www.xilinx.com 24PG054 July 25, 2012Product Specification
Transaction InterfaceTable 2-11:Physical Layer Interface SignalsName Direction Descriptionpl_initial_link_width[2:0] Output Initial Negotiated Link Width: Indicates the linkwidth after the PCI Express port has achieved thefirst successful link training. Initial Negotiated LinkWidth represents the widest link width possibleduring normal operation of the link, and can beequal to or smaller than the capability link width(smaller of the two) supported by link partners. Thisvalue is reset when the core is reset or the LTSSMgoes through the Detect state. Otherwise the valueremains the same.• 000: Link not trained• 001: 1-Lane link• 010: 2-Lane link• 011: 4-Lane link• 100: 8-Lane linkpl_phy_lnk_up Output Physical Layer Link Up Status: Indicates the physicallayer link up status.pl_lane_reversal_mode[1:0] Output Lane Reversal Mode: Indicates the current LaneReversal mode.• 00: No reversal• 01: Lanes 1:0 reversed• 10: Lanes 3:0 reversed• 11: Lanes 7:0 reversedpl_link_gen2_cap Output Link Gen2 Capable: Indicates that the PCI Expresslink is 5.0 Gb/s (Gen 2) speed capable (both the LinkPartner and the Device are Gen 2 capable)• 0: Link is not Gen2 Capable• 1: Link is Gen2 Capablepl_link_partner_gen2_supported Output Link Partner Gen2 Capable: Indicates if the PCIExpress link partner advertises 5.0 Gb/s (Gen2)capability. Valid only when user_lnk_up isasserted.• 0: Link partner not Gen2 capable• 1: Link partner is Gen2 capablepl_link_upcfg_cap Output Link Upconfigure Capable: Indicates the PCI Expresslink is Upconfigure capable. Valid only whenuser_lnk_up is asserted.• 0: Link is not Upconfigure capable• 1: Link is Upconfigure capablepl_sel_lnk_rate Output Current Link Rate: Reports the current link speed.Valid only when user_lnk_up is asserted.0: 2.5 Gb/s1: 5.0 Gb/s7 Series Integrated Block for PCIe (v1.6) www.xilinx.com 25PG054 July 25, 2012Product Specification
Page 1 and 2: 7 Series FPGAsIntegrated Block forP
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Appendix EAdditional ResourcesXilin
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Revision HistoryRevision HistoryThe
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