Xilinx PG054 7 Series FPGAs Integrated Block for PCI Express ...

Transaction InterfaceTable 2-18:User Application Error-Reporting Signals (Cont’d)Port Name Direction Descriptioncfg_err_locked Input Configuration Error Locked: This signal is used tofurther qualify any of the cfg_err_* input signals.When this input is asserted concurrently with one ofthe other signals, it indicates that the transaction thatcaused the error was a locked transaction.This signal is for use in Legacy mode. If the user needsto signal an unsupported request or an abortedcompletion for a locked transaction, this signal can beused to return a Completion Locked with UR or CAstatus.Note: When not in Legacy mode, the coreautomatically returns a Completion Locked, ifappropriate.cfg_err_aer_headerlog[127:0] Input Configuration Error AER Header Log: AER Header logfor the signalled error.cfg_err_aer_headerlog_set Output Configuration Error AER Header Log Set: Whenasserted, indicates that Error AER Header Log is Set inthe case of a Single Header implementation/Full in thecase of a Multi-Header implementation and theheader for user-reported error is not needed.cfg_aer_interrupt_msgnum[4:0] Input Configuration AER Interrupt Message Number: Thisinput sets the AER Interrupt Message (Root Port only)Number field in the AER Capability - Root Error Statusregister.If AER is enabled, this input must be driven to a valueappropriate for MSI or MSIx mode, whichever isenabled. This input value must be adjusted by the userif only MSI is enabled and the host adjusts the MultipleMessage Enable field such that it invalidates thecurrent value.cfg_err_acs Input Configuration Error ACS Violation: The user can assertthis signal to report that an ACS Violation hasoccurred.Notes:1. The user should assert these signals only if the device power state is D0. Asserting these signals in non-D0 devicepower states might result in an incorrect operation on the PCIe link. For additional information, see the PCI ExpressBase Specification, rev. 2.1, Section 5.3.1.2 [Ref 2].Table 2-19 defines the Error and Advanced Error Reporting Status of the 7 Series FPGAsIntegrated Block for PCI Express when configured as a Root Port.7 Series Integrated Block for PCIe (v1.6) www.xilinx.com 39PG054 July 25, 2012Product Specification