Xilinx PG054 7 Series FPGAs Integrated Block for PCI Express ...

Transaction InterfaceTable 2-17:cfg_pciecap_interrupt_msgnum[4:0] Input Configuration PCIe Capabilities - Interrupt MessageNumber: This input sets the Interrupt Message Numberfield in the PCI Express Capability register. This inputvalue must be adjusted by the user if only MSI is enabledand the host adjusts the Multiple Message Enable fieldsuch that it invalidates the current value.cfg_interrupt_stat Input Configuration Interrupt Status: Causes the InterruptStatus bit to be set or cleared when the automaticsetting of the Interrupt Status bit based on the InterruptInterface inputs is disabled.Error Reporting SignalsTable 2-18 defines the User Application error-reporting signals.Table 2-18:Configuration Interface Signals: Interrupt Interface - Endpoint Only (Cont’d)Name Direction DescriptionUser Application Error-Reporting SignalsPort Name Direction Descriptioncfg_err_ecrc Input ECRC Error Report: The user can assert this signal toreport an ECRC error (end-to-end CRC).cfg_err_ur Input Configuration Error Unsupported Request: The usercan assert this signal to report that an unsupportedrequest was received. This signal is ignored ifcfg_err_cpl_rdy is deasserted.cfg_err_cpl_timeout (1) Input Configuration Error Completion Timeout: The user canassert this signal to report a completion timed out.cfg_err_cpl_unexpect Input Configuration Error Completion Unexpected: The usercan assert this signal to report that an unexpectedcompletion was received.cfg_err_cpl_abort Input Configuration Error Completion Aborted: The user canassert this signal to report that a completion wasaborted. This signal is ignored if cfg_err_cpl_rdy isdeasserted.cfg_err_posted Input Configuration Error Posted: This signal is used tofurther qualify any of the cfg_err_* input signals. Whenthis input is asserted concurrently with one of theother signals, it indicates that the transaction thatcaused the error was a posted transaction.cfg_err_cor (1) Input Configuration Error Correctable Error: The user canassert this signal to report that a correctable error wasdetected.cfg_err_atomic_egress_blocked Input Configuration Error AtomicOp Egress Blocked: Theuser asserts this signal to report that an Atomic TLPwas blocked.7 Series Integrated Block for PCIe (v1.6) www.xilinx.com 37PG054 July 25, 2012Product Specification