Xilinx PG054 7 Series FPGAs Integrated Block for PCI Express ...

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Transaction InterfaceTable 2-11:Physical Layer Interface Signals (Cont’d)Name Direction Descriptionpl_sel_lnk_width[1:0] Output Current Link Width: Reports the current link width.Valid only when user_lnk_up is asserted.00: 1-Lane link01: 2-Lane link10: 4-Lane link11: 8-Lane linkpl_ltssm_state[5:0] Output LTSSM State: Shows the current LTSSM state (hex).0, 1: Detect Quiet2, 3: Detect Active4: Polling Active5: Polling Configuration6: Polling Compliance, Pre_Send_EIOS7: Polling Compliance, Pre_Timeout8: Polling Compliance, Send_Pattern9: Polling Compliance, Post_Send_EIOSA: Polling Compliance, Post_TimeoutB: Configuration Linkwidth, State 0C: Configuration Linkwidth, State 1D: Configuration Linkwidth, Accept 0E: Configuration Linkwidth, Accept 1F: Configuration Lanenum Wait10: Configuration Lanenum, Accept11: Configuration Complete x112: Configuration Complete x213: Configuration Complete x414: Configuration Complete x815: Configuration Idle16: L017: L1 Entry018: L1 Entry119: L1 Entry2 (also used for the L2/L3 Ready pseudostate)1A: L1 Idle1B: L1 Exit1C: Recovery Rcvrlock1D: Recovery Rcvrcfg7 Series Integrated Block for PCIe (v1.6) www.xilinx.com 26PG054 July 25, 2012Product Specification
Transaction InterfaceTable 2-11:Physical Layer Interface Signals (Cont’d)Name Direction Descriptionpl_ltssm_state[5:0] (Cont’d) Output 1E: Recovery Speed_01F: Recovery Speed_120: Recovery Idle21: Hot Reset22: Disabled Entry 023: Disabled Entry 124: Disabled Entry 225: Disabled Idle26: Root Port, Configuration, Linkwidth State 027: Root Port, Configuration, Linkwidth State 128: Root Port, Configuration, Linkwidth State 229: Root Port, Configuration, Link Width Accept 02A: Root Port, Configuration, Link Width Accept 12B: Root Port, Configuration, Lanenum_Wait2C: Root Port, Configuration, Lanenum_Accept2D: Timeout To Detect2E: Loopback Entry02F: Loopback Entry130: Loopback Active031: Loopback Exit032: Loopback Exit133: Loopback Master Entry0pl_rx_pm_state[1:0] Output RX Power Management State: Indicates the RX PowerManagement State:00: RX Not in L0s01: RX L0s Entry10: RX L0s Idle11: RX L0s FTSpl_tx_pm_state[2:0] Output TX Power Management State: Indicates the TX PowerManagement State:000: TX Not in L0s001: TX L0s Entry010: TX L0s Idle011: TX L0s FTS100 - 111: Reservedpl_directed_link_auton Input Directed Autonomous Link Change: Specifies thereason for directed link width and speed change.This must be used in conjunction withpl_directed_link_change[1:0],pl_directed_link_speed, andpl_directed_link_width[1:0] inputs.• 0: Link reliability driven• 1: Application requirement driven (autonomous)7 Series Integrated Block for PCIe (v1.6) www.xilinx.com 27PG054 July 25, 2012Product Specification
Page 1 and 2: 7 Series FPGAsIntegrated Block forP
Page 3: Chapter 5: Constraining the CoreReq
Page 6 and 7: SECTION I: SUMMARYIP FactsOverviewP
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ClockingWith these items implemente
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ClockingX-Ref Target - Figure 3-89P
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FPGA ConfigurationX-Ref Target - Fi
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FPGA Configuration100 ms ≤ T PWRV
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SECTION II: VIVADO DESIGN SUITECust
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GUIX-Ref Target - Figure 4-1Figure
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GUISelecting the alternate frequenc
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GUI• Type: BARs can either be I/O
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GUIID Initial Values• Vendor ID:
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Chapter 6Getting Started Example De
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Directory and File ContentsTable 6-
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Example DesignTable 6-5:sample_test
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Example DesignX-Ref Target - Figure
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Generating the Core1. Start the Viv
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SimulationX-Ref Target - Figure 6-1
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SECTION IV: APPENDICESMigratingDebu
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Migration ConsiderationsTable A-1:C
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Contacting Xilinx Technical Support
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Hardware DebugX-Ref Target - Figure
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Hardware Debugthat error detection
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Hardware Debug• Replay NUM Rollov
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Appendix CManaging Receive-Buffer S
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Methods of Managing Completion Spac
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Transaction Layer InterfaceTable D-
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Transaction Layer InterfaceTable D-
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GTX Transceiver InterfaceTable D-4:
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TL2 Interface PortsTable D-16: Debu
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Appendix EAdditional ResourcesXilin
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Revision HistoryRevision HistoryThe
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