Xilinx PG054 7 Series FPGAs Integrated Block for PCI Express ...

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PCI Configuration SpaceTable 2-22:Common PCI Configuration Space Header (Cont’d)31 16 15 0Link Status 2 Link Control 2 090hUnimplemented Configuration Space(Returns 0x00000000)094h-098hOptional MSlx Control NxtCap MSlx Cap 09ChTable OffsetPBA OffsetOptional (3) Next Cap Cap.Ver.Optional (3) Next Cap Cap.Ver.Reserved Legacy Configuration Space(Returns 0x00000000)PCI Express Device Serial Number (1st)PCI Express Device Serial Number (2nd)Port VC Capability Register 1Port VC Capability Register 2TableBIRPBABIRPCI Express Extended Capability - DSNPCI Express ExtendedCapability - VC0A0h0A4h0A8h-0FFh100h104h108h10Ch110h114hPort VC Status Port VC Control 118hOptional (3) Next Cap Cap.Ver.VC Resource Capability Register 0VC Resource Control Register 0VC Resource Status Register 0Vendor Specific HeaderVendor Specific - Loopback CommandVendor Specific - Loopback StatusVendor Specific - Error Count #1Vendor Specific - Error Count #2PCI Express Extended Capability - VSEC11Ch120h124h128h12Ch130h134h138h13Ch7 Series Integrated Block for PCIe (v1.6) www.xilinx.com 46PG054 July 25, 2012Product Specification
PCI Configuration SpaceTable 2-22:Common PCI Configuration Space Header (Cont’d)31 16 15 0Optional (3) Correctable Error Mask Register154hNext Cap Cap. Ver. PCI Express Extended Cap. ID (AER) 140hUncorrectable Error Status Register144hUncorrectable Error Mask Register148hUncorrectable Error Severity Register14ChCorrectable Error Status Register150hAdvanced Error Cap. & Control RegisterHeader Log Register 1Header Log Register 2Header Log Register 3Header Log Register 4158h15Ch160h164h168hOptional, Root Portonly (3) Root Error Status Register170hRoot Error Command Register 16ChError Source ID Register174hOptional (3) Reserved Resizable BAR Control(2) 190hNext Cap Cap. Ver. PCI Express Extended Cap. ID (RBAR) 178hResizable BAR Capability Register(0)17ChReserved Resizable BAR Control(0) 180hResizable BAR Capability Register(1)184hReserved Resizable BAR Control(1) 188hResizable BAR Capability Register(2)18ChResizable BAR Capability Register(3)194hReserved Resizable BAR Control(3) 198hResizable BAR Capability Register(4)19ChReserved Resizable BAR Control(4) 1A0hResizable BAR Capability Register(5)1A4hReserved Resizable BAR Control(5) 1A8hReserved Extended Configuration Space (Returns Completion with 0x00000000)1ACh-FFFhNotes:1. The MSI Capability Structure varies dependent on the selections in the CORE Generator tool GUI.2. Reserved for Endpoint configurations (returns 0x00000000).3. The layout of the PCI Express Extended Configuration Space (100h-FFFh) can change dependent on whichoptional capabilities are enabled. This table represents the Extended Configuration space layout when all fiveoptional extended capability structures are enabled. For more information, see Optional PCI Express ExtendedCapabilities, page 117.7 Series Integrated Block for PCIe (v1.6) www.xilinx.com 47PG054 July 25, 2012Product Specification
Page 1 and 2: 7 Series FPGAsIntegrated Block forP
Page 3: Chapter 5: Constraining the CoreReq
Page 6 and 7: SECTION I: SUMMARYIP FactsOverviewP
Page 8 and 9: Features (Continued)• Supports En
Page 10 and 11: Applications• Flow-control manage
Page 12 and 13: Standards ComplianceThe core uses p
Page 14 and 15: Available Integrated Blocks for PCI
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Page 18 and 19: Transaction InterfaceTransaction In
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General Design GuidelinesPower-supp
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ClockingWith these items implemente
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ClockingX-Ref Target - Figure 3-89P
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Protocol LayersProtocol LayersThe f
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FPGA ConfigurationThis section disc
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FPGA ConfigurationX-Ref Target - Fi
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FPGA Configuration100 ms ≤ T PWRV
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FPGA ConfigurationX-Ref Target - Fi
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SECTION II: VIVADO DESIGN SUITECust
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GUIX-Ref Target - Figure 4-1Figure
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GUISelecting the alternate frequenc
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GUI• Type: BARs can either be I/O
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GUIID Initial Values• Vendor ID:
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GUI• Extended Tag Field: Indicate
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GUIPinout SelectionThe Pinout Selec
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GUIX-Ref Target - Figure 4-13Transa
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GUI• Force No Scrambling: Used fo
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Output Generation/< component_name_
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Device, Package, and Speed Grade Se
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Core Timing ConstraintsPhysical con
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Supported Core PinoutsTable 5-2:Pac
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Chapter 6Getting Started Example De
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Directory and File ContentsTable 6-
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Example DesignTable 6-5:sample_test
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Example DesignX-Ref Target - Figure
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Generating the Core1. Start the Viv
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Generating the CoreX-Ref Target - F
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Generating the CoreX-Ref Target - F
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SimulationX-Ref Target - Figure 6-1
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Chapter 7Example Design and Model T
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Programmed Input/Output: Endpoint E
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Configurator Example Design• Conf
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SECTION III: ISE DESIGN SUITECustom
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GUISelecting the alternate frequenc
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Output Generation• Disable TX ASP
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Device, Package, and Speed Grade Se
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Supported Core PinoutsTable 10-2:Pa
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Example DesignX-Ref Target - Figure
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Generating the CoreFor help startin
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Simulation• routed.v[hd]Verilog o
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SECTION IV: APPENDICESMigratingDebu
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Migration ConsiderationsTable A-1:C
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Contacting Xilinx Technical Support
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Debug Tools• lspci -x -d []:[]Thi
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Hardware DebugX-Ref Target - Figure
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Hardware DebugFPGA Configuration Ti
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Hardware Debug• A component must
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Hardware Debug• Memory or I/O req
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Hardware Debugthat error detection
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Hardware Debug• Replay NUM Rollov
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Simulation Debug# [ 149143316] : TS
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Appendix CManaging Receive-Buffer S
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Methods of Managing Completion Spac
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Transaction Layer InterfaceTable D-
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Transaction Layer InterfaceTable D-
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Block RAM InterfaceTable D-2: Trans
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GTX Transceiver InterfaceTable D-4:
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Configuration Management InterfaceT
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TL2 Interface PortsTable D-16: Debu
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Appendix EAdditional ResourcesXilin
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Revision HistoryRevision HistoryThe
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