Xilinx PG054 7 Series FPGAs Integrated Block for PCI Express ...

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Transaction InterfaceTransaction InterfaceThe Transaction interface provides a mechanism for the user design to generate andconsume TLPs. The signal names and signal descriptions for this interface are shown inTable 2-7, Table 2-9, and Table 2-10.Common InterfaceTable 2-7 describes the common interface signals.Table 2-7: Common Transaction Interface SignalsName Direction Descriptionuser_clk_out Output Transaction Clock: Transaction, Configuration, and Physical LayerControl and Status Interface operations are referenced to andsynchronous with the rising edge of this clock. This signal is activeafter power-on, and sys_reset has no effect on it. This signal isguaranteed to be stable at the selected operating frequency onlyafter user_reset_out is deasserted. The user_clk_out clock outputis a fixed frequency configured in the CORE Generator tool. Thissignal does not change frequencies in case of link recovery ortraining down.See Table 2-8 for recommended and optional frequencies.user_reset_out Output Transaction Reset: User logic interacting with the Transaction andConfiguration interfaces must use user_reset_out to return to itsquiescent state. This signal is deasserted synchronously with respectto user_clk_out, and is deasserted and asserted asynchronouslywith sys_reset assertion. This signal is asserted for core in-bandreset events such as Hot Reset or Link Disable.user_lnk_up Output Transaction Link Up: Transaction link-up is asserted when the coreand the connected upstream link partner port are ready and able toexchange data packets. Transaction link-up is deasserted when thecore and link partner are attempting to establish communication, orwhen communication with the link partner is lost due to errors onthe transmission channel. This signal is also deasserted when thecore is driven to Hot Reset or Link Disable state by the link partner,and all TLPs stored in the core are lost. This signal is not deassertedwhile in the Recovery state, but is deasserted if Recovery fails.fc_ph[7:0] Output Posted Header Flow Control Credits: The number of Posted HeaderFC credits for the selected flow control type.fc_pd[11:0] Output Posted Data Flow Control Credits: The number of Posted Data FCcredits for the selected flow control type.fc_nph[7:0] Output Non-Posted Header Flow Control Credits: The number ofNon-Posted Header FC credits for the selected flow control type.fc_npd[11:0] Output Non-Posted Data Flow Control Credits: The number of Non-PostedData FC credits for the selected flow control type.7 Series Integrated Block for PCIe (v1.6) www.xilinx.com 18PG054 July 25, 2012Product Specification
Transaction InterfaceTable 2-7:Common Transaction Interface Signals (Cont’d)Name Direction Descriptionfc_cplh[7:0] Output Completion Header Flow Control Credits: The number of CompletionHeader FC credits for the selected flow control type.fc_cpld[11:0] Output Completion Data Flow Control Credits: The number of CompletionData FC credits for the selected flow control type.fc_sel[2:0] Input Flow Control Informational Select: Selects the type of flow controlinformation presented on the fc_* signals. Possible values:• 000: Receive buffer available space• 001: Receive credits granted to the link partner• 010: Receive credits consumed• 100: Transmit user credits available• 101: Transmit credit limit• 110: Transmit credits consumedTable 2-8:ProductRecommended and Optional Transaction Clock (user_clk_out) FrequenciesTransmit InterfaceLink Speed(Gb/s)Interface Width (1)(Bits)RecommendedFrequency (MHz)OptionalFrequency (MHz)1-lane 2.5 64 62.5 31.25, 125, 2501-lane 5 64 62.5 125, 2502-lane 2.5 64 62.5 125, 2502-lane 5 64 125 2504-lane 2.5 64 125 2504-lane 5 64 250 -4-lane 5 128 125 2508-lane 2.5 64 250 -8-lane 2.5 128 125 2508-lane 5 128 250 -Notes:1. Interface Width is a static selection and does not change with dynamic Link Speed changes.Table 2-9 defines the transmit (TX) interface signals. The bus s_axis_tx_tuser consists ofunrelated signals. Both the mnemonics and TSUSER signals are used throughout thisdocument. For example, the Transmit Source Discontinue signal is referenced as:(tsrc_dsc)s_axis_tx_tuser[3].7 Series Integrated Block for PCIe (v1.6) www.xilinx.com 19PG054 July 25, 2012Product Specification
Page 1 and 2: 7 Series FPGAsIntegrated Block forP
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Appendix EAdditional ResourcesXilin
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Revision HistoryRevision HistoryThe
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