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Xilinx PG054 7 Series FPGAs Integrated Block for PCI Express ...

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Transaction InterfaceTable 2-7:Common Transaction Interface Signals (Cont’d)Name Direction Descriptionfc_cplh[7:0] Output Completion Header Flow Control Credits: The number of CompletionHeader FC credits <strong>for</strong> the selected flow control type.fc_cpld[11:0] Output Completion Data Flow Control Credits: The number of CompletionData FC credits <strong>for</strong> the selected flow control type.fc_sel[2:0] Input Flow Control In<strong>for</strong>mational Select: Selects the type of flow controlin<strong>for</strong>mation presented on the fc_* signals. Possible values:• 000: Receive buffer available space• 001: Receive credits granted to the link partner• 010: Receive credits consumed• 100: Transmit user credits available• 101: Transmit credit limit• 110: Transmit credits consumedTable 2-8:ProductRecommended and Optional Transaction Clock (user_clk_out) FrequenciesTransmit InterfaceLink Speed(Gb/s)Interface Width (1)(Bits)RecommendedFrequency (MHz)OptionalFrequency (MHz)1-lane 2.5 64 62.5 31.25, 125, 2501-lane 5 64 62.5 125, 2502-lane 2.5 64 62.5 125, 2502-lane 5 64 125 2504-lane 2.5 64 125 2504-lane 5 64 250 -4-lane 5 128 125 2508-lane 2.5 64 250 -8-lane 2.5 128 125 2508-lane 5 128 250 -Notes:1. Interface Width is a static selection and does not change with dynamic Link Speed changes.Table 2-9 defines the transmit (TX) interface signals. The bus s_axis_tx_tuser consists ofunrelated signals. Both the mnemonics and TSUSER signals are used throughout thisdocument. For example, the Transmit Source Discontinue signal is referenced as:(tsrc_dsc)s_axis_tx_tuser[3].7 <strong>Series</strong> <strong>Integrated</strong> <strong>Block</strong> <strong>for</strong> <strong>PCI</strong>e (v1.6) www.xilinx.com 19<strong>PG054</strong> July 25, 2012Product Specification

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