Xilinx PG054 7 Series FPGAs Integrated Block for PCI Express ...

Transaction InterfaceTable 2-9: Transmit Interface Signals (Cont’d)Name Mnemonic Direction Descriptions_axis_tx_tuser[2] tx_str Input Transmit Streamed: Indicates a packet is presented onconsecutive clock cycles and transmission on the link canbegin before the entire packet has been written to thecore. Commonly referred as transmit cut-through mode.tx_cfg_req Output Transmit Configuration Request: Asserted when the coreis ready to transmit a Configuration Completion or otherinternally generated TLP.tx_cfg_gnt Input Transmit Configuration Grant: Asserted by the UserApplication in response to tx_cfg_req, to allow the core totransmit an internally generated TLP. The tx_cfg_reqsignal is always deasserted after the core-generatedpacket has been serviced before another request is made.Therefore, user designs can look for the rising edge oftx_cfg_req to determine when to assert tx_cfg_gnt.Holding tx_cfg_gnt deasserted after tx_cfg_req allowsuser-initiated TLPs to be given a higher priority oftransmission over core-generated TLPs. Assertingtx_cfg_gnt for one clock cycle when tx_cfg_req is assertedcauses the next packet output to be the core’s internallygenerated packet. In cases where there is no buffer spaceto store the internal packet, tx_cfg_req remains assertedeven after tx_cfg_gnt has been asserted. The user designdoes not need to assert tx_cfg_gnt again because theinitial assertion has been captured.If the user does not wish to alter the prioritization of thetransmission of internally generated TLPs, this signal canbe continuously asserted.s_axis_tx_tuser[1] tx_err_fwd Input Transmit Error Forward: This input marks the currentpacket in progress as error-poisoned. It can be assertedany time between SOF and EOF, inclusive. The tx_err_fwdsignal must not be asserted if (tx_str)s_axis_tx_tuser[2] isasserted.s_axis_tx_tuser[0] tx_ecrc_gen Input Transmit ECRC Generate: Causes the end-to-end cyclicredundancy check (ECRC) digest to be appended. Thisinput must be asserted at the beginning of the TLP.Receive InterfaceTable 2-10 defines the receive (RX) interface signals. The bus m_axis_tx_tuser consistsof unrelated signals. Mnemonics for these signals are used throughout this document inplace of the TUSER signal names.7 Series Integrated Block for PCIe (v1.6) www.xilinx.com 21PG054 July 25, 2012Product Specification