Xilinx PG054 7 Series FPGAs Integrated Block for PCI Express ...

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PCI Configuration SpaceThe core implements up to four legacy extended capability items. The remaining legacyextended capability space from address 0xA8 to 0xFF is reserved or user-definable(Endpoint configuration only). Also, the locations for any optional capability structure thatis not implemented are reserved. If the user does not use this space, the core returns0x00000000 when this address range is read. If the user chooses to implement registerswithin user-definable locations in the range 0xA8 to 0xFF, this space must be implementedin the User Application. The user is also responsible for returning 0x00000000 for anyaddress within this range that is not implemented in the User Application.For more information about enabling this feature, see Chapter 4, Customizing andGenerating the Core (Vivado Design Suite) or Chapter 9, Customizing and Generating theCore (ISE Design Suite). For more information about designing with this feature, see Designwith Configuration Space Registers and Configuration Interface, page 109.The core optionally implements up to three PCI Express Extended Capabilities. Theremaining PCI Express Extended Capability Space is available for users to implement. Thestarting address of the space available to the users depends on which, if any, of the fiveoptional PCIe Extended Capabilities are implemented. If the user chooses to implementregisters in this space, the user can select the starting location of this space, and this spacemust be implemented in the User Application. For more information about enabling thisfeature, see PCI Express Extended Capabilities, page 219 (Vivado Design Suite) or PCIExpress Extended Capabilities, page 311 (ISE Design Suite). For more information aboutdesigning with this feature, see Design with Configuration Space Registers andConfiguration Interface in Chapter 3.7 Series Integrated Block for PCIe (v1.6) www.xilinx.com 44PG054 July 25, 2012Product Specification
PCI Configuration SpaceTable 2-22:Common PCI Configuration Space Header31 16 15 0Device ID Vendor ID 000hStatus Command 004hClass Code Rev ID 008hBIST Header Lat Timer Cache Ln 00Ch010h014h018hHeader Type Specific(see Table 2-23 and Table 2-24)01Ch020h024h028h02Ch030hCapPtr034h038hIntr Pin Intr Line 03ChPM Capability NxtCap PM Cap 040hData BSE PMCSR 044hCustomizable (1) MSI Control NxtCap MSI Cap 048hMessage Address (Lower)Message Address (Upper)04Ch050hReserved Message Data 054hMask BitsPending Bits058h05ChPE Capability NxtCap PE Cap 060hPCI Express Device Capabilities064hDevice Status Device Control 068hPCI Express Link Capabilities06ChLink Status Link Control 070hRoot Port Only (2) Slot Capabilities 074hSlot Status Slot Control 078hRoot Capabilities Root Control 07ChRoot Status080hPCI Express Device Capabilities 2084hDevice Status 2 Device Control 2 088hPCI Express Link Capabilities 208Ch7 Series Integrated Block for PCIe (v1.6) www.xilinx.com 45PG054 July 25, 2012Product Specification
Page 1 and 2: 7 Series FPGAsIntegrated Block forP
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Appendix CManaging Receive-Buffer S
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Transaction Layer InterfaceTable D-
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Appendix EAdditional ResourcesXilin
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Revision HistoryRevision HistoryThe
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