RTL8181 Wireless LAN Access Point/Gateway Controller DATA ...

RTL8181*A=Analog signal*X=Not used .3. Address MappingThe RTL8181 supports up to 4 gigabytes of address space. The memory map of RTL8181 is managed by MMU, which willtranslate the virtual address to physical address. The memory is segmented into four regions by its access mode and cachingcapability as shown in following table.Segment Size Caching Virtual address range Physical address range ModeKUSEG 2048M cacheable 0x0000_0000-0x7fff_ffff set in TLB user/kernelKSEG0 512M cacheable 0x8000_0000-0x9fff_ffff 0x0000_0000-0x1fff_ffff kernelKSEG1 512M uncachable 0xa000_0000-0xbfff_ffff 0x0000_0000-0x1fff_ffff kernelKSEG2 512M cacheable 0xc000_0000-0xfeff_ffff set in TLB kernelKSEG2 512M cacheable 0xff00_0000-0xffff_ffff 0xff00_0000-0xffff_ffff kernelThe RTL8181 has two memory mapping modes: direct memory mapping and TLB (Translation Look-aside Buffer) addressmapping. When virtual address is located in the regions KSEG0, KSEG1 or higher half of KSEG2 segments, it physicaladdress will be mapped directly from virtual address with an offset. If virtual address used is in the regions of KUSEG orlower half of KSEG2 segment, its physical address will be referred from TLB entry. RTL8181 contains 16 TLB entries, eachof which maps to a page, with read/write access, cache-ability and process id.In RTL8181, SDRAM is mapped from physical address 0x0000_0000 to maximum 0x01ff_ffff (32M bytes). After reset,RTL8181 will start to fetch instructions from physical address 0x1fc0_0000, the starting address of flash memory. The flashmemory is mapped from physical address 0x1fc0_0000 to maximum 0x1fff_ffff (4M bytes).12CONFIDENTIAL v1.0