RTL8181 Wireless LAN Access Point/Gateway Controller DATA ...

RTL81810 23 BOVF Buffer Overflow. When set, indicates that receive buffer has everexhausted before this packet is received.0 22 FOVF FIFO Overflow. When set, indicates that FIFO overflow has everoccurred before this packet is received.0 21 RWT Receive Watchdog Timer expired. When set, indicates that the receivedpacket length exceeds 1724 bytes, the receive watchdog timer willexpire and stop receive engine.0 20 RES Receive Error Summary. When set, indicates at least one of thefollowing errors occurred: CRC, RUNT, RWT, FAE. This bit is validonly when LS(Last segment bit) is set0 19 RUNT Runt packet. When set, indicates that the received packet length issmaller than 64 bytes. RUNT packet is able to be received only whenRCR_AR is set.0 18 CRC CRC error. When set, indicates that a CRC error has occurred on thereceived packet. A CRC-error packet can be received only whenRCR_AER is set.0 17-16 PDI[1:0] Protocol ID1, Protocol ID000: Non-IP01: TCP/IP10: UDP/IP11: IP.0 15 IPF When set, indicates IP checksum failure.0 14 UDPF When set, indicates UDP checksum failure.0 13 TCPF When set, indicates TCP checksum failure.0 12-0 Frame_Le When OWN=0 and LS =1, it indicates the received packet lengthngth including CRC, in bytes.4 31-17 RSEV Reserved.4 16 TAVA Tag Available. When set, the received packet is an IEEE802.1Q VLANTAG (0x8100) available packet.4 15-0 VLAN_T If the packet ‘s TAG is 0x8100, The NIC extracts four bytes from afterAG source ID, sets TAVA bit to1, and moves the TAG value to this field inRx descriptor.8 31-0 RxBuff Logic Address of receive buffer.9. UART ControllerRTL8181 provides a 16C550 compatible UART, which contains 16 byte FIFOs. In addition, auto flow control is provided, inwhich, auto-CTS mode (CTS controls transmitter) and auto-RTS mode (Receiver FIFO contents and threshold control RTS)are both supported. The baud rate is programmable and allows division of any input reference clock by 1 to (2^16-1) andgenerates an internal 16x clock. RTL8181 provides fully programmable serial interface, which can be configured to support7,8 bit characters, even, odd, no parity generation and detection, and 1 or 2 stop bit generation. Last, fully prioritized interruptcontrol and loopback functionality for diagnostic capability are also provided.The clock source is 22MHz.UART Register SetVirtual address Size (byte) Name Description Access0xBD01_00C3 1 UART_RBR Receiver buffer register. (DLAB=0) R0xBD01_00C3 1 UART_THR Transmitter holding register. (DLAB=0) W0xBD01_00C3 1 UART_DLL Divisor latch LSB. (DLAB=1) R/W0xBD01_00C7 1 UART_IER Interrupt enable register. (DLAB=0) R/W0xBD01_00C7 1 UART_DLM Divisor latch MSB. (DLAB=1) R/W0xBD01_00CB 1 UART_IIR Interrupt identification register. R0xBD01_00CB 1 UART_FCR FIFO control register W0xBD01_00CF 1 UART_LCR Line control register R/W0xBD01_00D3 1 UART_MCR Modem control register R/W30CONFIDENTIAL v1.0