RTL8181 Wireless LAN Access Point/Gateway Controller DATA ...

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RTL81810xBD30_0014 4 ETH1_TSAD Transmit Starting Logic Address of R/WDescriptor0xBD30_0018 4 ETH1_RSAD Receive Starting Logic Address of R/WDescriptor0xBD30_0020 2 ETH1_IMR Ethernet0 Interrupt Mask Register R/W0xBD30_0024 2 ETH1_ISR Ethernet0 Interrupt Status Register R/W0xBD30_0028 4 ETH1_TMF0 Type match filter 0 register R/W0xBD30_002C 4 ETH1_TMF1 Type match filter 1 register R/W0xBD30_0030 4 ETH1_TMF2 Type match filter 2 register R/W0xBD30_0034 4 ETH1_TMF3 Type match filter 3 register R/W0xBD30_0038 4 ETH1_MII MII access register R/W0xBD30_003C 4 ETH1_CNR2 NIC control register 2 R/W0xBD30_0080 3 ETH1_MPC Ind icates the number of packets Rdiscarded due to rx FIFO overflow.It is a 24-bit counter. It is cleared tozero by read command.0xBD30_0084 2 ETH1_TXCOL Transmit collision counter. This R16-bit counter increments by 1 forevery collision event. It rolls overwhen becomes full. It is cleared tozero by read command.0xBD30_008C 2 ETH1_RXER Receive error count. This 16-bitcounter increments by 1 for eachvalid packet received . It is clearedto zero by read command.REthernet Control Register 1 (ETH0_CNR1, ETH1_CNR1)Bit Bit Name Description R/W InitVal31-29 RXBLEN Rx Burst length on Lexra bus.R/W 000000 - 010 = 64 bytes28-26 TXBLEN Tx Burst length on Lexra bus.R/W 000000 = 16 bytes001 = 32 bytes010 = 64 bytes25 FIFOAddrPtr FIFO Address Pointer: (Realtek internal use only R/W 0to test FIFO SRAM)0: Both Rx and Tx FIFO address pointers areupdated in ascending way from 0 and upwards.The initial FIFO address pointer is 0.1: Both Rx and Tx FIFO address pointers areupdated in descending way from 1FFh anddownwards. The initial FIFO address pointer is1FFh.24 TDFN Tx Descriptor Fetch Notify. Set this bit to notify W 0the NIC to fetch the Tx descriptors. The NIC willclear this bit automatically after all packets havebeen transmitted. Writing 0 to this bit has noeffect.20 RST Reset. A soft reset which disable the transmitter W 0and receiver, re-initializes the FIFOs, and bufferpointer to the initial value.19 RE Receiver enable. R/W 018 TE Transmitter enable. R/W 017 TxFCE Transmit flow control enable. R/W 016 RxFCE Receive flow control enable R/W 015 Reserved 014 RxVLAN Receive VLAN un-tagging enable R/W 013 RxChkSum Receive checksum offload enable R/W 022CONFIDENTIAL v1.0
RTL818112 FSWInt Forced software interrupt.WWriting 1 to this bit will trigger an interrupt, andthe SWIP bit will be set.The NIC will clear this bit automatically afterSWIP bit is cleared.Writing 0 to this bit has no effect.11-10 LBK[1:0] Loopback test. Setting both bits will route all R/W 00transmit traffic from Tx FIFO to Rx FIFO00: normal operation01, 10: reserved11: loopback mode9 NoCRC No CRC.R/W 00: CRC appended1: no CRC appended8 AER Accept error packets R/W 07 AB Accept Broadcast packets R/W 06 AM Accept Multicast packets R/W 05 APM Accept Physical address Matched packets R/W 04 AAP Accept All Physical packets R/W 03 ATM Accept Type match packets. This bit enables the R/W 0qualification of types of received packets.2 AR Accept runt packets R/W 01 ALEN Accept length specific packets. This bit is effective R/W 0when ATM bit is set.0: filter length specific packets.1: accept length specific packets.Ethernet Control Register 2 (ETH0_CNR2, ETH1_CNR2)Bit Bit Name Description R/W InitVal16 UAEN Unicast address filter enable (note).R/W 00: disabled. 1: enabled.15 TXPON Send Pause On packet. Write “1” to send Pause W 0On packet.14 TXPOFF Send Pause Off packet. Write “1” to send Pause W 0Off packet.13 TXPF Send Pause flag. Set, when NIC sends Pause-On R 0packet. Reset, when NIC sends Pause-Off packet.12 RXPF Receive Pause Flag: Set, when NIC is in backoff R 0state because a pause packet received. Reset, whenpause state is clear.11-8 PTMASK[3:0] Pause time mask. These bits mask the most R/W 1111significant four bits of pause time 0xFFFF usedfor a PAUSE packet. For example, ifPTMASK[3:0] is set to 0x01, a PAUSE packetwith pause time 0x1FFF will be sent whendescriptor unavailable condition occurs.6-4 IFG[2:0] InterFrameGap Time: This field allows the user to R/W 011adjust the interframe gap time longer than thestandard: 9.6 us for 10Mbps, 960 ns for 100Mbps.The time can be programmed from 9.6 us to 14.4us (10Mbps) and 960ns to 1440ns (100Mbps).The formula for the inter frame gap is011: 9.6us/ 960ns100: 9.6+4*0.1us/ 960+4*10ns101: 9.6+8*0.1us/ 960+8*10ns110: 9.6+12*0.1us/ 960+12*10ns111: 9.6+16*0.1us/ 960+16*10ns23CONFIDENTIAL v1.0
Page 1 and 2: RTL8181 Wireless LAN Access Point/G
Page 3 and 4: RTL8181Table of Contents1. OVERVIEW
Page 5 and 6: RTL8181Fast Ethernet Controller? Fu
Page 7 and 8: RTL8181WLTXRX O 64 T18 WLAN Tx/Rx t
Page 9 and 10: RTL8181TRSWN O 79 L20 Transmit and
Page 11 and 12: RTL8181TRDYBS/T/Scomplete the curre
Page 13 and 14: RTL8181Memory map (without TLB):Vir
Page 15 and 16: RTL81810xBD30_0014 ETH1_TSAD Ethern
Page 17 and 18: RTL818123 DISPCIB Disable PCI bridg
Page 19 and 20: RTL8181Besides, RTL8181could also s
Page 21: RTL8181The read access timing of fl
Page 25 and 26: RTL8181NIC to send PAUSE 0x0000 pac
Page 27 and 28: RTL81810 15-0 Frame_Le Transmit fra
Page 29 and 30: RTL81810 29-13 - Reserved.0 12-0 Bu
Page 31 and 32: RTL81810xBD01_00D7 1 UART_LSR Line
Page 33 and 34: RTL81817 DCD In loopback mode, retu
Page 35 and 36: RTL8181Bit Bit Name Description R/W
Page 37 and 38: RTL818129-28 PB14IM[1:0]31-30 PB15I
Page 39 and 40: RTL8181Bit Bit Name Description R/W
Page 41 and 42: RTL8181Transmit Configuration Regis
Page 43 and 44: RTL81810: Reject4 - Reserved3 AB Ac
Page 45 and 46: RTL8181Beacon Interval Register (WL
Page 47 and 48: RTL81813 SBQ Stop Beacon Queue: Wri
Page 49 and 50: RTL8181Package outline for 208 LQFP

RTL8181 Wireless LAN Access Point/Gateway Controller DATA ...

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