RTL8181 Wireless LAN Access Point/Gateway Controller DATA ...

RTL818123 DISPCIB Disable PCI bridge,0 enabe PCI bridge,1 R/W 0disable PCI bridge26-24 WLANCKR Bus clock to WLAN clock ratio. 000=1:1,001= R/W 1011:2,010=1:3,011=1:4,100=1:5,101=1:6,110=1:7,111=1:8. The WLAN maximum clock is40MHz.27 WLANCKRE WLANCKR write enable R/W 0N30-28 Reserved - - -31 DISWLANB Disable WLAN, 0 enabe WLAN,1 disableWLANR/W 0DPLL M,N parameter Register (PLLMN_REG)The DPLL clock rate is setting by this equation:44MHz*(M+1)/(N+1)Bit Bit Name Description R/W InitVal4-0 NDIV DPLL N parameter R/W 000117-5 Reserved - - -13-8 MDIV DPLL M parameter R/W 1001114 MNEN MDIV and NDIV write enable,0 disable ,1 R/W 0enable31-15 Reserved - - 0Memory parameterRegister (MEM_REG)Bit Bit Name Description R/W InitVal2-0 MEMDIV MEM clock ,000:DPLL/1, 001: DPLL/1.5, R/W 000010: DPLL/2,011:DPLL/2.5,100:DPLL/3,101:DPLL/4, 110:DPLL/6,111:DPLL/83 MEMDIVEN Enable MEMDIV writw,0 disable ,1 enable R/W 07-4 Reserved - - -CPU parameter Register (CPU_REG)Bit Bit Name Description R/W InitVal2-0 CPUDIV CPU clock ,000:DPLL/1, 001: DPLL/1.5, 010: R/W 000DPLL/2,011:DPLL/2.5,100:DPLL/3,101:DPLL/4, 110:DPLL/6,111:DPLL/83 CPUDIVEN Enable CPUDIV writw,0 disable ,1 enable R/W 07-4 Reserved - - -6. Interrupt ControllerRTL8181 provides six hardware-interrupt inputs IRQ0-IRQ5 internally. Some devices will share the same IRQ signal.Following table displays the IRQ map used by devices:IRQ Number Interrupt Source0 Timer/Counter interrupt1 GPIO/LBC interrupt2 WLAN interrupt3 UART/PCI interrupt4 Ethernet0 interrupt5 Ethernet1 interrupt17CONFIDENTIAL v1.0