RTL8181 Wireless LAN Access Point/Gateway Controller DATA ...

RTL81810xBD01_00D7 1 UART_LSR Line status register R/W0xBD01_00DB 1 UART_MSR Modem status register R/W0xBD01_00DF 1 UART_SCR Scratch register R/WInterrupt Enable Register (UART_IER)Bit Bit Name Description R/W InitVal7-6 - Reserved5 ELP Low power mode enable R/W 03 EDSSI Enable modem status register interrupt R/W 04 ESLP Sleep mode enable R/W 02 ELSI Enable receiver line status interrupt R/W 01 ETBEI Enable transmitter holding register empty interrupt R/W 00 ERBI Enable received data available interrupt R/W 0Interrupt Identification Register (UART_IIR)Bit Bit Name Description R/W InitVal7:5 FIFO64[2:0] 000 = no FIFOR 110110 = 16-byte FIFO4 - Reserved R 03:1 IID[2:0] Interrupt ID. IID[1:0] indicates the interruptpriority.0 IPND Interrupt pending0 = interrupt pendingInterrupt PriorityInterruptIdentification RegisterBit3 Bit2 Bit1 Bit0PrioritylevelInterrupt type Interrupt sourceR 000R 0Interrupt resetmethod0 0 0 1 None None None None0 1 1 0 1 Receiver line Overrun, parity, framing Read LSRstatus errors or break0 1 0 0 2 Received data DR bit is set.Read RBR.available1 1 0 0 2 Charactertime-outindicationNo characters have beenremoved from or input toFIFO during the last characterRead RBR0 0 1 0 3 Transmitterholding registeremptytimes and at 1 character in it.THRE bit set.Reading IIR or writeTHR0 0 0 0 4 Modem status CTS#,DSR#,RI#,DCD# Reading MSRFIFO Control Register (UART_FCR)Bit Bit Name Description R/W InitVal7-6 RTRG[1:0] Receiver trigger levelW 11Trigger level: 16-byte00 = 0101 = 0410 = 0811 = 143-5 - Reserved2 TFRST Transmitter FIFO reset. Writes 1 to clear the W 0transmitter FIFO.1 RFRST Receiver FIFO reset. Writes 1 to clear the receiver W 0FIFO.0 EFIFO Enable FIFO. When this bit is set, enable the W 031CONFIDENTIAL v1.0