RTL8181 Wireless LAN Access Point/Gateway Controller DATA ...

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RTL8181There are two registers for the interrupt control. The GIMR register can enable/disable the interrupt source. The GISR showsthe pending interrupt status.Interrupt Control Register SetVirtual address Size (byte) Name Description0xBD01_0000 2 GIMR Global interrupt mask register0xBD01_0004 2 GISR Global interrupt status registerGlobal Interrupt Mask Register (GIMR)Bit Bit Name Description R/W InitVal0 TCIE Timers/Counters interrupt enable.R/W 00: Disable, 1: Enable1 GPIOIE GPIO interrupt enable.R/W 00: Disable, 1: Enable2 WLAIE WLAN controller interrupt enable.R/W 00: Disable, 1: Enable3 UARTIE UART interrupt enable.R/W 00: Disable 1: Enable4 ETH0IE Ethernet0 interrupt enable.R/W 00: Disable, 1: Enable5 ETH1IE Ethernet1 interrupt enable.R/W 00: Disable, 1: Enable6 PCIIE PCI interrupt enable.R/W 00: Disable, 1: Enable7 Reserved8 LBC1E LBC time-out interrupt enable.0: Disable, 1: EnableR/W 0Global Interrupt Status Register (GISR)Bit Bit Name Description R/W InitVal0 TCIP Timers/Counters interrupt pending flag. R 00: no pending, 1: pending1 GPIOIP GPIO interrupt pending flag.R 00: no pending, 1: pending2 WLAIP WLAN controller interrupt pending flag. R 00: no pending, 1: pending3 UARTIP UARTI interrupt pending flag.R 00: no pending, 1: pending4 ETH0IP Ethernet0 interrupt pending flag.R 00: no pending, 1: pending5 ETH1IP Ethernet1 interrupt pending flag.R 00: no pending, 1: pending6 PCIIP PCI interrupt pending flag.R 00: no pending, 1: pending7 Reserved8 LBCIP LBC time-out interrupt pending flag.0: no pending, 1: pendingR 07. Memory ControllerRTL8181 provides a memory control module that could access external asynchronous SDRAM and flash memory.RTL8181 could interface to PC100 or PC133-compliant SDRAM, and supports with auto-refresh mode, which requires4096-cycle refresh in 64 ms. The SDRAM could be accessed in two banks (CS0#, and CS1#), and its size and timing areconfigurable in register. The data width of SDRAM could be chosen as 16-bit or 32-bit in register as well. If 32-bit isconfigured, 2 banks of 16-bit SDRAM may be used to expand its data width to 32 bits or use one bank of 32-bit SDRAM isallowable.18CONFIDENTIAL v1.0
RTL8181Besides, RTL8181could also supports two banks (F_CS0# and F_CS1#) access for flash memory. The system will always bootup from bank 0. The boot bank is mapped to KSEG1 and its beginning physical address at 0xBFC0_0000 (physical address:0x1FC0_0000). Bank 1 flash memory will be mapped to the address “0x1FC0_000 + flash size”. The flash size is configurablefrom 1M to 8M bytes for each bank. If flash size set to 4M or 8M the 0xBFC0_0000 still map the first 4M bytes of flash.There will have a new memory mapping from 0xBE00_0000. The 0xBE00_0000 mapped to the bank 0 byte 0.Memory Conf iguration Register SetVirtual address Size (byte) Name Description0xBD01_1000 4 MCR Memory Configuration Register0xBD01_1004 4 MTCR0 Memory Timing Configuration Register 00xBD01_1008 4 MTCR1 Memory Timing Configuration Register 1Note: These three registers should be accessed in double word.Memory Configuration Register (MCR)Bit Bit Name Description R/W InitVal.31-30 FLSIZE Flash size respective to one bank (byte).R/W 1100: 1M, 01: 2M, 10: 4M, 11:8M29-28 SDRSIZE SDRAM size respective to one bank (bit).R/W 0100: 512Kx16x2, 01: 1Mx16x4, 10: 2Mx16x4, 11:Reserved27 CAS CAS LatencyWR 00: Latency=2, 1: Latency=326-25 FLBK0BW Flash bank 0 bus width.R01: 16 bit24-23 FLBK1BW Flash bank 1 bus widthW/R 0100 11 10: reserved, 01: 16 bit22-21 - Reserved20 SDBUSWID SDRAM bus width0: 16 bit, 1: 32 bitW/R 1019 MCK2LCK Memory clock mode.Power on latch from GPIOB[13].1:Memory clockis the same as CPU clock. 0:memory clock following the power on latchfrom SYSCFG[3-0].R18-16 BUSCLK Bus Clock to control auto-refresh timingR/W 000000:200, 001:100, 010:50, 011:25, 100:12.5, 101:6.25110: 3.125, 111: 1.5625 MHz15-0 Reserved Must be set to bit value 00. R/W 00Memory Timing Configuration Register 0 (MTCR0)Bit Bit Name Description R/W InitVal31-28 CE0T_CS The timing interval between F_CE0# to WR#R/W 1111Basic unit, 2*clock cycle“0000” means 1 unit (2 clock cycles)27-24 CE0T_WP The timing interval for WR# to be pulled-lowR/W 1111Basic unit, 2*clock cycle“0000” means 1 unit (2 clock cycles)23-20 CE1T_CS The timing interval between F_CE1# to WR#R/W 1111Basic unit, 2*clock cycle“0000” means 1 unit (2 clock cycles)19-16 CE1T_WP The timing interval for WR# to be pulled-lowR/W 1111Basic unit, 2*clock cycle“0000” means 1 unit (2 clock cycles)15-0 - ReservedNote: The clock cycle is based memory clock.Memory Timing Configuration Register 1 (MTCR1)Bit Bit Name Description R/W InitVal19CONFIDENTIAL v1.0
Page 1 and 2: RTL8181 Wireless LAN Access Point/G
Page 3 and 4: RTL8181Table of Contents1. OVERVIEW
Page 5 and 6: RTL8181Fast Ethernet Controller? Fu
Page 7 and 8: RTL8181WLTXRX O 64 T18 WLAN Tx/Rx t
Page 9 and 10: RTL8181TRSWN O 79 L20 Transmit and
Page 11 and 12: RTL8181TRDYBS/T/Scomplete the curre
Page 13 and 14: RTL8181Memory map (without TLB):Vir
Page 15 and 16: RTL81810xBD30_0014 ETH1_TSAD Ethern
Page 17: RTL818123 DISPCIB Disable PCI bridg
Page 21 and 22: RTL8181The read access timing of fl
Page 23 and 24: RTL818112 FSWInt Forced software in
Page 25 and 26: RTL8181NIC to send PAUSE 0x0000 pac
Page 27 and 28: RTL81810 15-0 Frame_Le Transmit fra
Page 29 and 30: RTL81810 29-13 - Reserved.0 12-0 Bu
Page 31 and 32: RTL81810xBD01_00D7 1 UART_LSR Line
Page 33 and 34: RTL81817 DCD In loopback mode, retu
Page 35 and 36: RTL8181Bit Bit Name Description R/W
Page 37 and 38: RTL818129-28 PB14IM[1:0]31-30 PB15I
Page 39 and 40: RTL8181Bit Bit Name Description R/W
Page 41 and 42: RTL8181Transmit Configuration Regis
Page 43 and 44: RTL81810: Reject4 - Reserved3 AB Ac
Page 45 and 46: RTL8181Beacon Interval Register (WL
Page 47 and 48: RTL81813 SBQ Stop Beacon Queue: Wri
Page 49 and 50: RTL8181Package outline for 208 LQFP

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