RTL8181 Wireless LAN Access Point/Gateway Controller DATA ...

More documents

Recommendations

Info

RTL8181000: 9.6+20*0.1us/ 960+20*10ns001: 9.6+24*0.1us/ 960+24*10ns010: 9.6+48*0.1us/ 960+48*10ns3-0 TXRR[3:0] Tx Retry Count: These are used to specify R/W 0additional transmission retries in multiple of16(IEEE 802.3 CSMA/CD retry count). If theTXRR is set to 0, the transmitter will re-transmit16 times before aborting due to excessivecollisions. If the TXRR is set to a value greaterthan 0, the transmitter will re-transmit a number oftimes equals to the following formula beforeaborting: Total retries = 16 + (TXRR * 16)The TER bit in the ISR register or transmitdescriptor will be set when the transmission failsand reaches to this specified retry count.Note: Bit UAEN is only existed in ETH0_CNR2 register.Unicast Address Filter Register (ETH0_UAR)Bit Bit Name Description R/W InitVal127-0 UARTBL Unicast address hash table. If the ‘n’ bit value is R/W 0set ‘1’, it implies the receiving frames which hashvalue with ‘n’ will be indicated.Interrupt Mask Register (ETH0_IMR, ETH1_IMR)Bit Bit Name Description R/W InitVal9 LINKCHGIE Link status changed interrupt enable R/W 08 RERIE Rx error interrupt enable R/W 07 TERIE Tx error interrupt enable R/W 06 ROKIE ROK interrupt enable. A descriptor reception is R/W 0completed successfully.5 TOKIE TOK interrupt enable. A descriptor transmission is R/W 0completed successfully.4 RFOVWIE Rx FIFO overflow interrupt enable R/W 03 RDUIE Rx descriptor unavailable interrupt enable. Set R/W 0when the Rx Descriptors have been exhausted.2 Reserved1 TDUIE Tx descriptor unavailable interrupt enable R/W 00 SWIE Software interrupt enable R/W 0Interrupt Status Register (ETH0_ISR, ETH1_ISR)Bit Bit Name Description R/W InitVal9 LINKCHGIP Link status changed interrupt pending flag. Write R/W 0“1” to clear the interrupt.8 RERIP Rx error interrupt pending flag. Write “1” to clear R/W 0the interrupt.7 TERIP Tx error interrupt enable flag. Write “1” to clear R/W 0the interrupt.6 ROKIP ROK interrupt pending. A descriptor reception is R/W 0completed successfully. Write “1” to clear theinterrupt.5 TOKIP TOK interrupt pending. A descriptor transmission R/W 0is completed successfully. Write “1” to clear theinterrupt.4 RFOVWIP Rx FIFO overflow interrupt pending Write “1” to R/W 0clear the interrupt..3 RDUIP Rx descriptor unavailable interrupt pending. Setwhen the Rx Descriptors have been exhausted.Write “1” to clear the interrupt and it also triggerR/W 024CONFIDENTIAL v1.0
RTL8181NIC to send PAUSE 0x0000 packet.2 Reserved1 TDUIP Tx descriptor unavailable interrupt pending flag.Write “1” to clear the interrupt.0 SWIP Software interrupt pending flag. Write “1” to clearthe interrupt.R/W 0R/W 0MII Access Register (ETH0_MII, ETH1_MII)Bit Bit Name Description R/W InitVal31-22 - Reserved21 MMIMODE Mode of MII management interface. (Realtek R/W 0internal use only to test 3-port switch)0 = auto mode. The NIC controls MDC and MDIOpins. Setting this bit will trigger anauto-negotiation if DisNway bit is cleared.1 = manual mode. The software controls MDC andMDIO pins.20-16 PHYAD[4:0] PHY address. R/W 0x0115 LinkCtrl Link control.R/W 00: force link down.1: force link up.14 DplxCtrl Duplex control. When DuplexCtrl bit is cleared, R/W 1this bit is read only. The NIC will poll its localPHY regularly. This bit will reflect the result ofauto-negotiation from its local PHY. If FDuplex isset, this bit is writable. The software may programthe bit and force the MII operates in full-duplex orhalf-duplex mode.0: Force half-duplex mode.1: Force full-duplex mode.13 SpdCtrl Speed control.R/W 10: 10Mbps1: 100Mbps.12 FlCtrl Flow control.R/W 00:disable flow control.1: enable flow control.11 LinkSt Link status. This bit reflects the link status from its R 0local PHY.0: link down1: link up10 DuplexSt Duplex status. This bit reflects the duplex status R 0from its local PHY.0: half duplex9 SpeedSt Speed status. This bit reflects the link speed from R 0its local PHY.0: 10Mbps1: 100Mbps8 FlCtrlSt Flow control statusR 00: flow control disabled1: flow control enabled.7-5 - Reserved4 DisNway Disable N-way0: auto-negotiation mode.The local PHY willadvertise its capability per the settings ofDplxCtrl, SpdCtrl, and FlCtrl bits.1: forced mode (disable N-way). The softwaremay force MII operating mode by writing thecorresponding value to the DplxCtrl, LinkCtrl,SpdCtrl,FlCtrl bits.R/W 025CONFIDENTIAL v1.0
Page 1 and 2: RTL8181 Wireless LAN Access Point/G
Page 3 and 4: RTL8181Table of Contents1. OVERVIEW
Page 5 and 6: RTL8181Fast Ethernet Controller? Fu
Page 7 and 8: RTL8181WLTXRX O 64 T18 WLAN Tx/Rx t
Page 9 and 10: RTL8181TRSWN O 79 L20 Transmit and
Page 11 and 12: RTL8181TRDYBS/T/Scomplete the curre
Page 13 and 14: RTL8181Memory map (without TLB):Vir
Page 15 and 16: RTL81810xBD30_0014 ETH1_TSAD Ethern
Page 17 and 18: RTL818123 DISPCIB Disable PCI bridg
Page 19 and 20: RTL8181Besides, RTL8181could also s
Page 21 and 22: RTL8181The read access timing of fl
Page 23: RTL818112 FSWInt Forced software in
Page 27 and 28: RTL81810 15-0 Frame_Le Transmit fra
Page 29 and 30: RTL81810 29-13 - Reserved.0 12-0 Bu
Page 31 and 32: RTL81810xBD01_00D7 1 UART_LSR Line
Page 33 and 34: RTL81817 DCD In loopback mode, retu
Page 35 and 36: RTL8181Bit Bit Name Description R/W
Page 37 and 38: RTL818129-28 PB14IM[1:0]31-30 PB15I
Page 39 and 40: RTL8181Bit Bit Name Description R/W
Page 41 and 42: RTL8181Transmit Configuration Regis
Page 43 and 44: RTL81810: Reject4 - Reserved3 AB Ac
Page 45 and 46: RTL8181Beacon Interval Register (WL
Page 47 and 48: RTL81813 SBQ Stop Beacon Queue: Wri
Page 49 and 50: RTL8181Package outline for 208 LQFP

RTL8181 Wireless LAN Access Point/Gateway Controller DATA ...

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?