RTL8181 Wireless LAN Access Point/Gateway Controller DATA ...

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RTL81811: Enable0: Disable3 TLPDER Tx Low Priority Descriptor Error Interrupt:1: Enable0: Disable2 TLPDOK Tx Low Priority Descriptor OK Interrupt:1: Enable0: Disable1 RER Rx Error Interrupt:1: Enable0: Disable0 ROK Rx OK Interrupt:1: Enable0: DisableR/WR/WR/WR/WInterrupt Status Register (WLAN_ISR)This register indicates the source of WLAN controller interrupt goes active. Enabling the corresponding bits in the InterruptMask Register (WLAN_IMR) allows bits in this register to produce an interrupt. When an interrupt is active, one of more bitsin this register are set to a “1”. The interrupt Status Register reflects all current pending interrupts, regardless of the state of thecorresponding mask bit in the WLAN_IMR. Reading the WLAN_ISR clears all interrupts. Writing a 1 to any bit in thisregister will reset that bit.Bit Symbol Description R/W15 TXFOVW Tx FIFO Overflow R/W14 TimeOut Time Out: This bit is set to 1 when the least 32 bits of the TSFTR register reaches to the R/Wvalue of the TimerInt register.13 BcnInt Beacon Time Out Interrupt: When set, this bit indicates that the TBTT (Target Beacon R/WTransmission Time) has been reached after the value of the Beacon interrupt Intervalregister.12 ATIMInt ATIM Time Out Interrupt: When set, this bit indicates that the ATIM window has been gone R/Wafter the value of the Beacon interrupt Interval register.11 TBDER Transmit Beacon Priority Descriptor Error: Indicates that a packet of beacon priority descriptor R/Wtransmission was aborted due to an Rx beacon frame.10 TBDOK Transmit Beacon Priority Descriptor OK: Indicates that a packet of beacon priority R/Wdescriptor exchange sequence has been successfully completed.9 THPDER Transmit High Priority Descriptor Error: Indicates that a packet of high priority descriptor R/Wtransmission was aborted due to an SSRC (Station Short Retry Count) has reached SRL(Short Retry Limit), and an SLRC (Station Long Retry Count) has reached LRL (Long RetryLimit).8 THPDOK Transmit High Priority Descriptor OK: Indicates that a packet of high priority descriptor R/Wexchange sequence has been successfully completed.7 TNPDER Transmit Normal Priority Descriptor Error: Indicates that a packet of normal priority R/Wdescriptor transmission was aborted due to an SSRC (Station Short Retry Count) hasreached SRL (Short Retry Limit), and an SLRC (Station Long Retry Count) has reachedLRL (Long Retry Limit).6 TNPDOK Transmit Normal Priority Descriptor OK: Indicates that a packet of normal priority R/Wdescriptor exchange sequence has been successfully completed.5 FOVW Rx FIFO Overflow: This bit set to 1 is caused by RDU, poor PCI performance, or R/Woverloaded PCI traffic.4 _RDU Rx Descriptor Unavailable: When set, this bit indicates that the Rx descriptor is currently R/Wunavailable.3 TLPDER Transmit Low Priority Descriptor Error: Indicates that a packet of low priority descriptor R/Wtransmission was aborted due to an SSRC (Station Short Retry Count) has reached SRL(Short Retry Limit), and an SLRC (Station Long Retry Count) has reached LRL (Long RetryLimit).2 TLPDOK Transmit Low Priority Descriptor OK: Indicates that a packet of low priority descriptor R/Wexchange sequence has been successfully completed.1 RER Receive Error: Indicates that a packet has a CRC32 or ICV error. R/W0 ROK Receive OK: In normal mode, indicates the successful completion of a packet reception. R/W40CONFIDENTIAL v1.0
RTL8181Transmit Configuration Register (WLAN_TCR)This register defines the Transmit Configuration for the WLAN controller. It controls such functions as loopback, heartbeat,auto transmit padding, programmable inter-frame gap, fill and drain thresholds, and maximum DMA burst size.Bit Symbol Description R/W31 CWMIN Contention Window minimum value: Set to 1 to indicate that Cwmin=8. Set to 0 to indicate R/Wthat Cwmin=32.30 SEQGEN Sequence number generation switch.0 – Enabled. Sequence number is generated by RTL8181.1 – Disabled. Sequence number should be filled by software.29-25 - Reserved24 SAT Set ACK Timeout: The EIFS, ACK and CTS timeouts are derived from the following R/Wequation:EIFS = 112/ACKrate + 2521: ACKrate is dependent on the maximum of MBR (bits 1:0, BRSR) and Rx DATA/RTSrate.0: ACKrate is fixed at 1Mbps.23-21 MXDMA2, 1, Max DMA Burst Size per Tx DMA Burst: This field sets the maximum size of transmit R/W0DMA data bursts according to the following table:000: 16 bytes001: 32 bytes010: 64 bytes011: 128 bytes100: 256 bytes101: 512 bytes110: 1024 bytes111: 2048 bytes20 DISCW Disable Contention Window Backoff: This bit indicates the existence of a backoff procedure R/Wduring packet transmission.1: No random backoff procedure0: Uses IEEE 802.11 random backoff procedure19 ICV Append ICV: This bit indicates the existence of ICV appended at the end of an encipherment R/Wpacket.1: No ICV appended0: ICV appended18-17 LBK1, LBK0 Loopback Test: There will be no packet on the TXI+/- and TXQ+/- lines under the R/WLoopback test condition. The loopback function must be independent of the link state.00: Normal operation01: MAC Loopback10: Baseband Loopback11: Continue TX.16 CRC Append CRC32: This bit indicates the existence of a CRC32 appended at the end of a R/Wpacket.1: No CRC32 appended0: A CRC32 is appended15-8 SRL RTS Retry Limit: Indicates the maximum retry times of RTS frame, data or management R/Wframe of length less than or equal to RTSThreshold.7-0 LRL Data Packet Retry Limit: Indicates the maximum retransmission times of Data orManagement frame of length greater than RTSThreshold.R/WReceive Configuration Register (WLAN_RCR)This register is used to set the receive configuration for the WLAN controller. Receive properties such as accepting errorpackets, runt packets, setting the receive drain threshold etc. are controlled here.Bit Bit Name Description R/W31 ONLYERLP Early Receiving based on Packet Size: Early Receiving is only performed for packets with a R/WKT size greater than 1536 bytes.30 ENCS2 Enable Carrier Sense Detection Method 2 R/W41CONFIDENTIAL v1.0
Page 1 and 2: RTL8181 Wireless LAN Access Point/G
Page 3 and 4: RTL8181Table of Contents1. OVERVIEW
Page 5 and 6: RTL8181Fast Ethernet Controller? Fu
Page 7 and 8: RTL8181WLTXRX O 64 T18 WLAN Tx/Rx t
Page 9 and 10: RTL8181TRSWN O 79 L20 Transmit and
Page 11 and 12: RTL8181TRDYBS/T/Scomplete the curre
Page 13 and 14: RTL8181Memory map (without TLB):Vir
Page 15 and 16: RTL81810xBD30_0014 ETH1_TSAD Ethern
Page 17 and 18: RTL818123 DISPCIB Disable PCI bridg
Page 19 and 20: RTL8181Besides, RTL8181could also s
Page 21 and 22: RTL8181The read access timing of fl
Page 23 and 24: RTL818112 FSWInt Forced software in
Page 25 and 26: RTL8181NIC to send PAUSE 0x0000 pac
Page 27 and 28: RTL81810 15-0 Frame_Le Transmit fra
Page 29 and 30: RTL81810 29-13 - Reserved.0 12-0 Bu
Page 31 and 32: RTL81810xBD01_00D7 1 UART_LSR Line
Page 33 and 34: RTL81817 DCD In loopback mode, retu
Page 35 and 36: RTL8181Bit Bit Name Description R/W
Page 37 and 38: RTL818129-28 PB14IM[1:0]31-30 PB15I
Page 39: RTL8181Bit Bit Name Description R/W
Page 43 and 44: RTL81810: Reject4 - Reserved3 AB Ac
Page 45 and 46: RTL8181Beacon Interval Register (WL
Page 47 and 48: RTL81813 SBQ Stop Beacon Queue: Wri
Page 49 and 50: RTL8181Package outline for 208 LQFP

RTL8181 Wireless LAN Access Point/Gateway Controller DATA ...

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