RTL8181 Wireless LAN Access Point/Gateway Controller DATA ...

RTL8181transmitter and receiver FIFOs. Changing this bitclears the FIFOs.Line Control Register (UART_LCR)Bit Bit Name Description R/W InitVal7 DLAB Divisor latch access bit. R/W 06 BRK Break control. Set this bit force TXD to the R/W 0spacing (low) state.(break) Clear this bit to disablebreak condition.5-4 EPS[1:0] Even parity selectR/W 000 = odd parity01 = even parity10 = mark parity11 = space parity3 PEN Parity enable R/W 02 STB Number of stop bitsR/W 00 = 1 bit1 = 2 bits1-0 WLS[1:0] Word length select10 = 7 bits11 = 8 bitsR/W 11Modem Control Register (UART_MCR)Bit Bit Name Description R/W InitVal7-6 - Reserved5 AFE Auto flow control enable R/W 04 LOOP Loopback R/W 02-3 - Reserved1 RTS Request to sendR/W 00 = Set RTS# high1 = Set RTS# low0 - ReservedLine Status Register (UART_LSR)Bit Bit Name Description R/W InitVal7 RFE Errors in receiver FIFO. At least one parity, R 0framing and break error in the FIFO.6 TEMT Transmitter emptyR 0Character mode: both THR and TSR are empty.FIFO mode: both transmitter FIFO and TSR areempty5 THRE Transmitter holding register empty.R 0Character mode: THR is empty.FIFO mode: transmitter FIFO is empty4 BI Break interrupt indicator R 03 FE Framing error R 02 PE Parity error R 01 OE Overrun error. An overrun occurs when the R 0receiver FIFO is full and the next character iscompletely received in the receiver shift register.An OE is indicated. The character in the shiftregister will be overwritten.0 DR Data ready.Character mode: data ready in RBRFIFO mode: receiver FIFO is not empty.R 0Modem Status Register (UART_MSR)Bit Bit Name Description R/W InitVal32CONFIDENTIAL v1.0