Architecture Modeling - SPES 2020

Architecture Modeling
The architecture platform is represented by a gate library which contains different types of
logical gates, each with its cost related to area, speed and power consumption. The mapping
process selects a set of interconnected gates from the gate library such that the functionality
of the network is the same as the one represented by the RTL. To optimize the gate selection
process, the semantic domain of the RTLs is first restricted to synchronous designs. Then,
the RTL is translated into Boolean expressions; the same semantic domain is chosen for the
gates in the library. To ease the gate selection process, both the Boolean equations and the gate
library are transformed into net-lists consisting of a primitive logical gate, such as a NAND2.
At this point, mapping, known in logic synthesis as technology mapping, is then reduced to a
minimum cost covering problem. Since optimal covering is NP-hard, heuristic algorithms are
used. Note that this mapping process is based on a common primitive - NAND2 gate - and
mathematical rules for defining the behavior of a set of interconnected primitives - Boolean
logic. Boolean logic is appropriate for synthesizing combinational logic between registers in
a synchronous hardware design. Hence, the process involves three aspects: restriction of the
functional domain to synchronous circuits, choosing a common mathematical representation
(Boolean expressions), and representing the functionality and architecture platform in terms of
primitives (NAND2).
We believe that these three aspects can be generalized and used to help solve any mapping
problem at system level. In the general system setting, however, each of these three aspects is
challenging. The models of computation used in system design are varied and certainly more
complex than Boolean logic with synchronous timing. The selection of a common mathematical
language for both the functionality and the architecture platform depends on critical decisions
involving expressiveness and ease of manipulation. Finally, selecting the primitive elements to
use involves a trade-off between granularity and optimality: coarser granularity allows the use
of exhaustive search techniques that may guarantee optimality while finer granularity allows the
possibility of exploring, albeit non-optimally, a much larger search space.
The formal mapping procedure is shown in Figure 5.24. Initially, we are given function and
architecture models, which are constructed from the functional specification and architecture
platform. During Stage 1 of the procedure, a common modeling domain (CMD) is chosen by
the designers for representing the functionality and architecture (platform). When choosing a
proper CMD, both the semantics and abstraction level for mapping are decided by considering
the trade-off between the size of the mapping space and the complexity of finding a good point
within this space. In Stage 2, a CMD-specific covering problem is formulated and solved by
automatic algorithms. Stage 3 is added to capture all further optimization that may be needed
to tune the design. It includes design concerns that have not been modeled within the covering
problem formulation because they make the solution of the covering problem too complex.
5.2.5 Managing Risk
The realization of complex systems calls for design processes that mitigate risks in highly concurrent,
distributed, and typically multi-domain engineering processes, often involving more
than one hundred sub-processes. Risk mitigation measures typically cover all phases of design
processes, ranging from assuring high quality initial requirements to early assessments of risks
in realizability of product requirements during the concept phase, to enforcing complete traceability
of such requirements with requirements management tools, to managing consistency and
synchronization across concurrent sub-processes using PLM tools. The topic of achieving high
quality of initial requirements has already been addressed above.
A key challenge rests in balancing risk reduction version development time and effort. For
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