Architecture Modeling - SPES 2020

Architecture Modeling
Figure 5.9: Technical Perspective – System Level
identifier. In Section 5.1.3.3 we show for a similar allocation-link how its validity may be
proven by a virtual integration test.
Realization When performing the design step from one abstraction level to the next (lower)
one, a realize-link (as introduced in Section 4.4.3) has to be established to ensure a valid refinement
step. To give an understanding of the idea how a system (part) is realized at a lower
abstraction level, the technical perspective at the Device Level is shown in Figure 5.12.
At this level, the BSCU is realized by three resource components: itsBSCUSelector,
itsBSCUMonCom1, and itsBSCUMonCom2. The reason for splitting the BSCU is due to the
decision to provide the system with redundant command and monitor units to meet safety requirements
(no single point of failure in the BSCU). These can be found in itsBSCUMonCom1
and itsBSCUMonCom2 respectively. The itsBSCUSelector, a combinational logic modeled
as a device resource, selects and forwards the signals to the driver unit of the appendant
actuator. For simplicity, the communication between these three components is represented by
an abstract signal for each component rather than the explicit modeling of the actual signals. In
this snapshot, a contract is shown with a more complex guarantee that contains implications.
The guarantee consists of two parts, each depicted in a blue box, that are connected by a conjunction
∧ (not shown in the figure). The implication is used here to model different modes of
the system i.e. the normal mode in the upper box where the itsBSCUSelector component
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