Architecture Modeling - SPES 2020

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Architecture Modeling resumeEvent is a flow of kind event. The direction is always out. The referenced flow shall be triggered by some Scheduler or forwarded by some SchedulerSlot, when access to the processing capacities of a scheduled resource has been granted and suspended before and now access to the ProcessingResource is granted again. This reference to a flow is only needed, if preemption can occur. Port + isConjugated: Boolean SchedulerPort 1 {redefines type} +type SchedulerPortSpec «isOfT ype» SchedulerPPort SchedulerRPort +activateEvent 1 «isOfT ype» + direction: FlowDirection + kind: FlowKind PortSpecification +finEvent 1 +startEvent 1 +resumeEvent 0..1 +suspendEvent 0..1 Figure 3.12: Meta-model integration of the concept SchedulerPort +type 1 Flow +comSpec +schedulerEvent 3..5 In a model the scheduling of a ProcessingResource will look like depicted in Figure 3.13. The ports marked in red color are SchedulerPorts. The figure also shows how to make use of the Scheduler and SchedulerSlot concepts when modeling the hierarchical scheduling of a ProcessingResource. A SchedulerSlot can also serve a second Scheduler, which then only distributes the capacity of the ProcessingResource to its clients that it receives through its underlying slot by the main scheduler. ProcessingResource :Concurrency Resource :Concurrency Resource :SchedulerSlot :SchedulerSlot :Scheduler :SchedulerSlot :Scheduler :Concurrency Resource :SchedulerSlot Figure 3.13: Example of using the Scheduler concept ComputingResources: The concept ComputingResource shown in Figure 3.14 models a processing device capable of storing and executing Tasks. This concept is an abstraction of elements of an execution platform hosting multiple tasks, which require computing capacity in order to carry out their computations. Being derived from ProcessingResource a ComputingResource may be subject to scheduling of its computing capacity. The Task concept models a computation task. As it is derived from ConcurrencyResource, it can be connected to a SchedulerSlot, thus using the 24/ 156
Architecture Modeling computing capacity the SchedulerSlot receives from a Scheduler. In the role executionTime a Task can aggregate multiple declarations of its execution time, that has been measured/analysed. Provided a task would have exclusive access to a ComputingResource the execution time is the time from starting the task until it finishes. As the execution time may vary depending on the kind of the computing device, one can specify multiple execution times, each with a unique identifier. An example specification of an execution time, would be: {ARM7;500us;1ms}. Where 500us is the best base execution time and 1ms is the worst case execution time. RichComponent Resource + isActive: Boolean + isProtected: Boolean + resMult: int [0..1] = 1 Task ConcurrencyResource ProcessingResource SchedulerSlot +executionT ime SchedulerPort SchedulerRPort 0..* +required 0..* Constant ExecutionTimeSpec ComputingResource SchedulerPort SchedulerPPort +provided 0..* + isPreemptible: Boolean = true Figure 3.14: Meta-model integration of the concept ComputingResource CommunicationResources: The concept CommunicationResource shown in Figure 3.15 models an abstraction of a communication device of an execution platform capable of transferring information from one location to another. The attributes of CommunicationResource are used to describe its most relevant properties needed for timing analysis of a technical architecture. Being derived from ProcessingResource a CommunicationResource may be subject to scheduling of its communication capacity. A frame is a data item, which is transmitted by a CommunicationResource. The concept FrameTriggering models the triggering and identification of a frame transmitted by a CommunicationResource. As the concept is derived from ConcurrencyResource, it can be connected to a SchedulerSlot, thus using the communication capacity the SchedulerSlot receives from a Scheduler. SchedulerPort +required SchedulerRPort 0..* ConcurrencyResource FrameTriggering Resource Resource ProcessingResource + transmMode: T ransmModeKind CommunicationResource SchedulerSlot Resource + isPreemptible: Boolean = true +provided SchedulerPort 0..* SchedulerPPort Figure 3.15: Meta-model integration of the concept CommunicationResource Describing data encapsulation in communication stacks: We consider the technical architecture as a network of ComputingResources, that are interconnected by means of CommunicationResources. The frames, that are transmitted by that CommunicationResources are however not the data items, that would be sent directly by some application task. Instead in most execution platforms an application programming 25/ 156
Page 1 and 2: Architecture Modeling ∗ Andreas B
Page 3 and 4: Contents 1 Introduction 1 2 Quick-T
Page 5 and 6: 1 Introduction This document propos
Page 7 and 8: Architecture Modeling allowing to m
Page 9 and 10: Architecture Modeling creating a vi
Page 11 and 12: Architecture Modeling the design it
Page 13 and 14: Architecture Modeling of the logica
Page 15 and 16: Architecture Modeling realization o
Page 17 and 18: Architecture Modeling can usually o
Page 19 and 20: 3 The Architecture Meta-Model In Se
Page 21 and 22: Abstraction-Levels (detail increase
Page 23 and 24: 3.2.2 Functional Perspective Archit
Page 25 and 26: Architecture Modeling The semantics
Page 27: Architecture Modeling expressed by
Page 31 and 32: 3.2.5 Geometrical Perspective Archi
Page 33 and 34: ShapeCompositionOperator intersecti
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Page 37 and 38: Architecture Modeling of particular
Page 39 and 40: Architecture Modeling Shape that de
Page 41 and 42: Architecture Modeling Conjugation o
Page 43 and 44: RichComponent Architecture Modeling
Page 45 and 46: MultiplicityElement +part 0..* Rich
Page 47 and 48: ComponentC Architecture Modeling pa
Page 49 and 50: 4 Steps in Component-Based Design T
Page 51 and 52: Architecture Modeling Assume/guaran
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Page 59 and 60: established if (and only if): Archi
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Page 63 and 64: Architecture Modeling The component
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Page 71 and 72: 5 Using the Architecture Meta-Model
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Architecture Modeling Figure 5.4: O
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Architecture Modeling Figure 5.7: L
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Architecture Modeling Figure 5.9: T
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Architecture Modeling Figure 5.12:
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Architecture Modeling However this
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Architecture Modeling The considera
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Architecture Modeling tasks Command
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Architecture Modeling of the V, suc
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Architecture Modeling thus decorate
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Architecture Modeling In summary, P
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Architecture Modeling OEMs are incr
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Architecture Modeling provide effec
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Architecture Modeling patterns, cap
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Architecture Modeling 6.1 Syntax an
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6.1.1.1.1 Attribuute Definit tion a
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Constrrain Eventts with Co ondition
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These events used in the “and the
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Formalization: whenever StartButton
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Architecture Modeling Basic bloock
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6.1.1.1.1.3 Conditions Conditions c
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6.1.1.1.2.2 Seammless Con ncatenati
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e3 && (clk==0) e1 idle pre e1 idle
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Pattern whenever event occurs condi
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If the brake force is above 80% for
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Pattern S3: Failure shall not be ca
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Pattern S9: failureCondition failur
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Pattern R2: Event occurs each perio
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idle e1 |clk:=0 e2 && (l
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The function : allocates a singl
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Examplees of clocks: • Run: {c=0@
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Architecture Modeling 1. For σ ∈
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Architecture Modeling Traces accord
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Architecture Modeling Definition 6.
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Architecture Modeling the one given
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Architecture Modeling Decomposition
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Bibliography [1] ARINC 653 - Avioni
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Architecture Modeling [26] Holger G
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Architecture Modeling - SPES 2020

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