Architecture Modeling - SPES 2020

Architecture Modeling
the organization of the overall computer system, in terms of CPUs, MMUs, bus-systems, I/O,
caches, memory etc. Note that this layering also motivates the wording of “abstraction layers”.
In fact, different design styles for integrated circuits are characterized by what abstraction
level is taken as a design basis. E.g., in gate-level design, a higher degree of automation is
achieved by taking gates as primitives (from a design library), while full-custom design processes
capitalize on the capabilities of building custom complex gates from transistors, and
most notably from the capability of optimizing the layout of individual transistors to optimize
performance. In contrast, in gate-level design, the internal realization of employed gates is
completely hidden, and designs are build purely based on characterization of such standards
cells as given in design libraries. Note also, that the type of underlying computational models
differs drastically between design levels. As an example, differential equations are used as
models to characterize how the transistor current is dependent on various parameters such as
the gate-to-source voltage, or the drain-to-source voltage. In contrast, at gate level design, such
continuos dynamics are abstracted to a boolean, discrete time domain, e. g. for gates and other
combinational circuits to boolean functions and maximal and minimal propagation delays.
Perspectives (in EDA jargon: domains) are orthogonal to these. The geometric perspective
(in the EDA domain, sometimes also called “physical domain”) speaks about the physical realization
of the integrated cuircuit. E.g. on the transistor level, the physical dimensions of all
materials used to realized transistors, such as the gate’s aspect ratio, the thickness of the insulation
layer below the gate, the extension of drain and source, but as well the routing of wires
on the layers of the integrated circuits and their physical dimensions etc. are described in a
standardized way allowing automatic production of the integrated circuit. With increasing integration
density, the system-level, which in the 80’s would talk about placement of ICs and their
interconnections on the printed cuircuit board, has moved to the level of on-chip positioning of
multiple processor cores, on-chip interconnection networks, on-chip cache hierarchies, etc. In
short, the geometric perspective covers all abstraction layers, and allows to physically build the
complete system, using the blue-prints or the physical realization of lower abstraction levels.
The information of what components, then, are to be built, and, in particular, how they are
connected comes from the technical perspective. Here, the focus is on architecture: how can
we architect a modern processor from RT-primitives supporting multiple-issue of instructions,
out-of-order execution of multiple instructions using multiple functional units and multi-port
register files, etc. This design is typically done not only using abstraction (that is, through the
concept of abstraction layers), but also by disregarding the physical realization of the system,
i. e. the geometrical perspective. This conscious choice of (initially) ignoring the geometric domain
comes with a price: clearly extra-functional characteristics of the integrated cuircuit are
highly dependent on the physical layout, and thus any analysis e. g. of timing aspects is only
indicative, since it typically ignores propagation delays induced by routing, and delay characteristics
of library elements are based on assumptions on capacities which can only be checked
in the physical domain. Yet, in spite of these caveats, and the lack of a formally establishable
link between extra-functional aspects in the technical perspective and the counterpart in the
physical perspective, industrial practice shows, that the productivity gains obtained by initially
disregarding the impact of the geometric domain by far outweigh the costs coming from patches
required to compensate for non-tolerable changes in such characteristics.
Finally, the behavioral domain is used, at each of the above abstraction layers, to capture the
specification of what the component of the circuit should do. Examples include the specification
of an instruction-set architecture, of caches, of a multiplier, of a complex gate, or, at the lowest
level, “Kennlinien”, i. e. curves characterizing the desired dependency of the drain-to-source
current in terms of other parameters.
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