Architecture Modeling - SPES 2020

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Architecture Modeling allows to model execution platforms hosting the components of the logical perspective. Here resource limitations come into play, e. g. the sharing of computing resources by multiple logical components. The behavior of the allocated logical components will therefore depend on the properties of the resource as well as the other logical components allocated to the very same resource. 3.2.4.1 Resources The concepts of the metamodel for specifying the technical perspective of a system are inspired by the UML Profile for MARTE (Modeling and Analysis of Real-Time Embedded Systems) [40]. RichComponent Resource + isActive: Boolean + isProtected: Boolean + resMult: int [0..1] = 1 StorageResource +elem entSize 1 ConcurrencyResource ProcessingResource SchedulerSlot + isPreemptible: Boolean = true Dev iceResource ComputingResource CommunicationResource + transmMode: T ransm ModeKind +packetT ime 1 Expression +elementSize 1 +blockingT ime 1 Scheduler + isPreemptible: Boolean = true +capacity 1 +schedule 1 TextuallyRepresentedElement Figure 3.10: Meta-model integration of the concepts of Resources The concept Resource shown in Figure 3.10 constitute an abstraction of the resources a platform provides and allocated behaviour from logical components. Examples for resource are: • computational resources, i. e. the computational power of some processor • bandwidth of a communication resource • storage capacity of a storage resource As some of those resources might be shared by multiple consumers, this sharing of resources can be explicated by means of schedulers. Such a scheduler distributes fractions of a resource according to a given scheduling strategy. The concept Scheduler allows for modelling static as well as dynamic scheduler types. Schedulers: The concept Scheduler depicted in Figure 3.11 distributes fractions of a resource according to a given strategy. The clients of a scheduler are modeled by the concept SchedulerSlot. The Resource, whose capacity is shared and assigned by a scheduler is 22/ 156
Architecture Modeling expressed by the concept ProcessingResource. The SchedulingPolicy concept allows to specify the strategy of the scheduler, e. g. fixed-priority based. The SchedulerSlots, which receive a fraction of the resource, aggregate the concept SchedParameterSpec, that specifies parameters used by a scheduler to run its strategy. Such parameters are for example the definition of a priority. RichComponent Resource + isActive: Boolean + isProtected: Boolean + resMult: int [0..1] = 1 +required SchedulerPort SchedulerRPort +required ConcurrencyResource ProcessingResource SchedulerSlot 0..* + isPreem ptible: Boolean = true Variable SchedParameterSpec +provided SchedulerPort SchedulerPPort +provided 0..1 +required 1 +provided 0..* 0..* +schedParameters 1 1..* Scheduler + isPreemptible: Boolean = true +policy 1 +schedule 1 TextuallyRepresentedElement Expression +scheduleLength 0..1 SchedulingPolicy + otherSchedPolicy: String [0..1] + policy: SchedPolicyKind = FixedPriority Figure 3.11: Meta-model integration of the concept Scheduler The concept, which actually uses the fraction of the ProcessingResource, is a ConcurrencyResource or specializations thereof. If some schedule was determined offline, it can be directly specified by means of an Expression in the role schedule. This overrides whatever was specified in the SchedulingPolicy. The relation of the concepts Scheduler, SchedulerSlot and ConcurrencyResource is modeled by the special ports SchedulerPPort and SchedulerRPort. That ports must be typed by a PortSpecification, which is conformant to the concept SchedulerPortSpec (see Figure 3.12). This specification comprises five flows, that are referenced in the following roles: activateEvent is a flow of kind event. The direction is always in. This event denotes the request for the activation of a ConcurrencyResource. The ConcurrencyResource thus notifies its need to access the capacity of a ProcessingResource. startEvent is a flow of kind event. The direction is always out. This event denotes the grant of some Scheduler upon a previously received request (the activateEvent). finEvent is a flow of kind event. The direction is always in. This event denotes the release of the capacity of the ProcessingResource by the ConcurrencyResource. It is triggered, when the ConcurrencyResource has finished its computation or communication. suspendEvent is a flow of kind event. The direction is always out. The referenced flow shall be triggered by some Scheduler or forwarded by some SchedulerSlot, when access to the processing capacities of a scheduled resource has been granted before, but shall now be revoked in favour of another SchedulerSlot. This reference to a flow is only needed, if preemption can occur. 23/ 156
Page 1 and 2: Architecture Modeling ∗ Andreas B
Page 3 and 4: Contents 1 Introduction 1 2 Quick-T
Page 5 and 6: 1 Introduction This document propos
Page 7 and 8: Architecture Modeling allowing to m
Page 9 and 10: Architecture Modeling creating a vi
Page 11 and 12: Architecture Modeling the design it
Page 13 and 14: Architecture Modeling of the logica
Page 15 and 16: Architecture Modeling realization o
Page 17 and 18: Architecture Modeling can usually o
Page 19 and 20: 3 The Architecture Meta-Model In Se
Page 21 and 22: Abstraction-Levels (detail increase
Page 23 and 24: 3.2.2 Functional Perspective Archit
Page 25: Architecture Modeling The semantics
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Page 31 and 32: 3.2.5 Geometrical Perspective Archi
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Page 39 and 40: Architecture Modeling Shape that de
Page 41 and 42: Architecture Modeling Conjugation o
Page 43 and 44: RichComponent Architecture Modeling
Page 45 and 46: MultiplicityElement +part 0..* Rich
Page 47 and 48: ComponentC Architecture Modeling pa
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Page 59 and 60: established if (and only if): Archi
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Page 71 and 72: 5 Using the Architecture Meta-Model
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Architecture Modeling Figure 5.9: T
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Architecture Modeling Figure 5.12:
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Architecture Modeling However this
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Architecture Modeling The considera
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Architecture Modeling tasks Command
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Architecture Modeling of the V, suc
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Architecture Modeling thus decorate
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Architecture Modeling In summary, P
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Architecture Modeling OEMs are incr
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Architecture Modeling provide effec
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Architecture Modeling patterns, cap
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Architecture Modeling 6.1 Syntax an
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6.1.1.1.1 Attribuute Definit tion a
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Constrrain Eventts with Co ondition
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These events used in the “and the
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Formalization: whenever StartButton
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Architecture Modeling Basic bloock
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6.1.1.1.1.3 Conditions Conditions c
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6.1.1.1.2.2 Seammless Con ncatenati
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e3 && (clk==0) e1 idle pre e1 idle
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Pattern whenever event occurs condi
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If the brake force is above 80% for
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Pattern S3: Failure shall not be ca
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Pattern S9: failureCondition failur
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Pattern R2: Event occurs each perio
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idle e1 |clk:=0 e2 && (l
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The function : allocates a singl
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Examplees of clocks: • Run: {c=0@
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Architecture Modeling 1. For σ ∈
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Architecture Modeling Traces accord
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Architecture Modeling Definition 6.
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Architecture Modeling the one given
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Architecture Modeling Decomposition
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Bibliography [1] ARINC 653 - Avioni
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Architecture Modeling [26] Holger G
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Architecture Modeling - SPES 2020

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