Architecture Modeling - SPES 2020

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temp occurs each 50ms Delay between temp and control within [20ms,25ms] Architecture Modeling Mapping Technical Perspective tempVal temp temp Data control Var1 ECU Capture Task Scheduler Figure 4.11: Mapping: Proof Obligations airTemp CtrlTask havior of the mapping provides the necessary conversion in order to reason about the intended refinement relation between both representations of the component. Due to internal behavior of the mapping, confidence of the result of a refinement check also depends on the faithfulness of the mapping. For sake of traceability, mappings can be associated with contracts to allow formal specification of their behavior. When proof obligations are violated during the design process, mapping contracts may give means to reason about the faithfulness of the chosen behavior of the involved mappings. € € temp ∈ IN temp = 4⋅ temp 2 + 2⋅ temp 1 + temp 0 € temp0 ,temp1 ,temp2 ∈{0,1} Capture AirTempSystem tempData control AirTempControl Figure 4.12: Mapping with Interface Refinement Two properties are essential when dealing with mappings: Completeness Contracts are always associated to components. More precisely, contracts are restricted to reason about the interface of the associated component. In order to obtain welldefined relations between contracts, mappings are required to establish port relations that are complete with respect to all associated contracts. If for example in Figure 4.10, only the right port of component AirTempSystem would be linked to the mapping, the component could not be replaced without provoking inconsistency of the model. Receptiveness Mappings are required to be receptive. Their internal behavior must not restrict any contracts of the observed model. control Var2 tempSel 64/ 156
Architecture Modeling Another important issue when dealing with mappings is locality. Since there are no constraints in the number of mappings to link certain models, it should be best practice to keep the number of linked ports for a mapping as low as possible. The benefit it twofold: on one hand, locality maintains traceability on the relation between contracts of different models. On the other hand, it supports also locality of the respective proof obligations. However, each mapping must be verified. 4.4.2 Allocation While mappings provide the common concept to establish traceability in a design, the SPESMM provides two instantiations of this concept. An allocate link associates two components within different perspectives. The intuition of an allocate link is that the source component is “executed” by the target component of the link. A function is executed by a logical component, and a logical component is executed by a technical component. The intuition also holds if we say that a technical component is “executed” by a box in the geometrical perspective. The allocate link is a high-level construct in that for each link an underlying mapping is created. Each allocate link thus requires further specification with respect the underlying mapping. In many cases however, simple mapping functions are sufficient to define allocations. SPESMM allows to refine allocate links by additional links specifying simple one-to-one relations between ports, and by textual specification of such one-to-one relations within the mapping object. Figure 4.13 depicts an example for using the allocate link. The link shown allocates logical component Capture to task CaptureTask in the technical perspective. The link is associated to a mapping object that has been further refined (not shown in the figure) to specify that the respective ports are directly linked. Logical Perspective temp tempData Capture 4.4.3 Realization AirTempControl control Technical Perspective tempVal temp temp Data control Var1 ECU Capture Task Figure 4.13: Allocate-Link Example Scheduler airTemp CtrlTask The second high-level construct are realize links that associate components between different abstraction levels. Since the realize link is the twin of the allocate link, the same holds as said before. Note however, that the direction of both allocate and realize links are converse. For realize links, the source component by convention associates the observed components with respect to Var2 tempSel 65/ 156
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Architecture Modeling ∗ Andreas B
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Contents 1 Introduction 1 2 Quick-T
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1 Introduction This document propos
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Architecture Modeling allowing to m
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Architecture Modeling creating a vi
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Architecture Modeling the design it
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Architecture Modeling of the logica
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Architecture Modeling realization o
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Page 21 and 22: Abstraction-Levels (detail increase
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Page 25 and 26: Architecture Modeling The semantics
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These events used in the “and the
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Formalization: whenever StartButton
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Architecture Modeling Basic bloock
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6.1.1.1.1.3 Conditions Conditions c
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6.1.1.1.2.2 Seammless Con ncatenati
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e3 && (clk==0) e1 idle pre e1 idle
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Pattern whenever event occurs condi
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If the brake force is above 80% for
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Pattern S3: Failure shall not be ca
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Pattern S9: failureCondition failur
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Pattern R2: Event occurs each perio
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idle e1 |clk:=0 e2 && (l
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The function : allocates a singl
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Architecture Modeling 1. For σ ∈
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Architecture Modeling Traces accord
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Architecture Modeling Definition 6.
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Architecture Modeling the one given
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Architecture Modeling Decomposition
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Bibliography [1] ARINC 653 - Avioni
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Architecture Modeling [26] Holger G
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