Architecture Modeling - SPES 2020

More documents

Recommendations

Info

Architecture Modeling the underlying mapping, while for allocation links, the observed components is denoted by the link target. temp AirTempSystem temp tempData Capture control AirTempControl control Figure 4.14: Realize-Link Example 66/ 156
5 Using the Architecture Meta-Model Design processes for embedded systems applications differ strongly within the range of application domains considered in SPES 2020. In automation applications, the geometric layout of the plant is determined early in planning stages, and defines boundary conditions for other design phases. In contrast, while of course medical devices such as pace-makers must ultimately fit into a physical packaging easily insertable into the body, other aspects such as algorithm design are more dominant. Similarly, almost no industrial application will be developed purely top-down, nor purely bottom-up, and tradeoffs such as between optimizing re-use and optimizing for performance will determine the middle-out design strategy for a particular product development. Finally, target architectures are often subject to domain specific standards, such as AUTOSAR [9] in the automotive domain, and IMA in avionics, calling for a need to support a variety of domain specific standards within the SPES Architecture Metamodel. The purpose of this section can thus not be to describe something as “the SPES design process”. Rather, the purpose of this section is to show how a broad variety of design styles and design processes can be naturally expressed using the key concepts of the SPES Architecture Metamodel. An orthogonal aspect covered in this section relates to the advocation of a contract-based design style. We highlight, how typical design steps in industrial processes can benefit from contract-based design, thus motivating the anchoring of this design paradigm in the SPES metamodel. We cover these orthogonal aspects in separate sections. The style of writing is chosen so as to address a typical systems engineer. Having read the quick tour (Section 2) is an indispensable prerequisite for this section. Readers who are interested in more formal treatments of the mentioned design steps are referred to Section 4 – “Steps in component based design” – and its mathematical foundation given in the annex. 5.1 On the Role of Perspectives and Abstraction Layers 5.1.1 What We Can Learn from the EDA Domain Electronic design automation (EDA) has early adopted the concept of abstraction layers (to cope with complexity) and perspectives (there called “domains”) to achieve separation of concerns between different views of an integrated circuit, such as its physical layout, its logical architecture, and its behavior (see Gajski’s Y-Chart [25]). Established abstraction levels include (from lower to higher) the transistor level, the gate level, the register transfer level, the system level, and the instruction-set architecture level. Each level is essentially characterized by what is seen as a primitive building block at the chosen level of abstraction. The identity of the building block is obvious from the level name for the transistor and the gate level. For the register transfer level, these blocks include both combinational circuits such as adders, multipliers, shifters, etc., as well as sequential circuits such as latches, registers, register-files, and the various types of memory. The naming of the next higher level is predominantly used in the domain of computer architecture design, where clock-cycle accurate models describe the effect of executing instructions on the visible processor state. The term system-level, then, traditionally referred to 67/ 156
Page 1 and 2:
Architecture Modeling ∗ Andreas B
Page 3 and 4:
Contents 1 Introduction 1 2 Quick-T
Page 5 and 6:
1 Introduction This document propos
Page 7 and 8:
Architecture Modeling allowing to m
Page 9 and 10:
Architecture Modeling creating a vi
Page 11 and 12:
Architecture Modeling the design it
Page 13 and 14:
Architecture Modeling of the logica
Page 15 and 16:
Architecture Modeling realization o
Page 17 and 18:
Architecture Modeling can usually o
Page 19 and 20: 3 The Architecture Meta-Model In Se
Page 21 and 22: Abstraction-Levels (detail increase
Page 23 and 24: 3.2.2 Functional Perspective Archit
Page 25 and 26: Architecture Modeling The semantics
Page 27 and 28: Architecture Modeling expressed by
Page 29 and 30: Architecture Modeling computing cap
Page 31 and 32: 3.2.5 Geometrical Perspective Archi
Page 33 and 34: ShapeCompositionOperator intersecti
Page 35 and 36: Architecture Modeling The constrain
Page 37 and 38: Architecture Modeling of particular
Page 39 and 40: Architecture Modeling Shape that de
Page 41 and 42: Architecture Modeling Conjugation o
Page 43 and 44: RichComponent Architecture Modeling
Page 45 and 46: MultiplicityElement +part 0..* Rich
Page 47 and 48: ComponentC Architecture Modeling pa
Page 49 and 50: 4 Steps in Component-Based Design T
Page 51 and 52: Architecture Modeling Assume/guaran
Page 53 and 54: Architecture Modeling When specifyi
Page 55 and 56: Architecture Modeling next selectio
Page 57 and 58: Architecture Modeling ports must ha
Page 59 and 60: established if (and only if): Archi
Page 61 and 62: 12°C < tempSelect < 35°C actTemp
Page 63 and 64: Architecture Modeling The component
Page 65 and 66: Architecture Modeling 4.3.2 Establi
Page 67 and 68: Architecture Modeling a mapping is
Page 69: Architecture Modeling Another impor
Page 73 and 74: Architecture Modeling Design proces
Page 75 and 76: Architecture Modeling abstraction l
Page 77 and 78: Pwr1 Pedal_Pos1 Pwr2 Pedal_Pos2 CMD
Page 79 and 80: Architecture Modeling Figure 5.4: O
Page 81 and 82: Architecture Modeling Figure 5.7: L
Page 83 and 84: Architecture Modeling Figure 5.9: T
Page 85 and 86: Architecture Modeling Figure 5.12:
Page 89 and 90: Architecture Modeling However this
Page 91 and 92: Architecture Modeling The considera
Page 97 and 98: Architecture Modeling tasks Command
Page 99 and 100: Architecture Modeling of the V, suc
Page 101 and 102: Architecture Modeling thus decorate
Page 103 and 104: Architecture Modeling In summary, P
Page 105 and 106: Architecture Modeling OEMs are incr
Page 107 and 108: Architecture Modeling provide effec
Page 111 and 112: Architecture Modeling patterns, cap
Page 113 and 114: Architecture Modeling 6.1 Syntax an
Page 115 and 116: 6.1.1.1.1 Attribuute Definit tion a
Page 117 and 118: Constrrain Eventts with Co ondition
Page 119 and 120: These events used in the “and the
Page 121 and 122:
Formalization: whenever StartButton
Page 123 and 124:
Architecture Modeling Basic bloock
Page 125 and 126:
6.1.1.1.1.3 Conditions Conditions c
Page 127 and 128:
6.1.1.1.2.2 Seammless Con ncatenati
Page 129 and 130:
e3 && (clk==0) e1 idle pre e1 idle
Page 131 and 132:
Pattern whenever event occurs condi
Page 133 and 134:
If the brake force is above 80% for
Page 135 and 136:
Pattern S3: Failure shall not be ca
Page 137 and 138:
Pattern S9: failureCondition failur
Page 139 and 140:
Pattern R2: Event occurs each perio
Page 141 and 142:
idle e1 |clk:=0 e2 && (l
Page 143 and 144:
The function : allocates a singl
Page 145 and 146:
Examplees of clocks: • Run: {c=0@
Page 147 and 148:
Architecture Modeling 1. For σ ∈
Page 149 and 150:
Architecture Modeling Traces accord
Page 151 and 152:
Architecture Modeling Definition 6.
Page 153 and 154:
Architecture Modeling the one given
Page 155 and 156:
Architecture Modeling Decomposition
Page 157 and 158:
Bibliography [1] ARINC 653 - Avioni
Page 159 and 160:
Architecture Modeling [26] Holger G
show all

Architecture Modeling - SPES 2020

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?