Architecture Modeling - SPES 2020

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6.1.1.5 Mapping Pattern Mapping patterns can be used to express the requirements on the mapping from the functional design perspective to the physical design perspective. Functions are mapped to hardware elements. Pattern M1: [under condition (condition)] function function-set shall [not] be mapped to hw-element-set. This pattern specifies that a set of functions shall [not] be mapped to a set of hardware elements. A function set consists of multiple functions concatenated with “AND” or “OR”. A hardware element set can consist of multiple hardware elements concatenated with “OR”. The condition can consist of other mapping constraints like “a is mapped together with b” Natural Language Requirement: The functions a and b shall not be allocated to RDCa2. Pattern based RSL: function a OR b shall not be mapped to RDCa2. Pattern M2: [under condition (condition)] function function-set shall [not] be mapped together with function-set. This pattern specifies that a set of functions shall [not] be mapped together to a hardware element with another function set. A function set consists of multiple functions concatenated with “AND” or “OR”. The condition can consist of other mapping constraints like “a is mapped together with b” Natural Language Requirement: The functions a and b shall not be allocated to the RDC where the function c is allocated to. Pattern based RSL: function a OR b shall not be mapped together with c. Pattern M3: Architecture Modeling [under condition (condition)] function function-set shall [not] be mapped to same target. This pattern specifies that a set of functions shall [not] be mapped to the same hardware element. A function set consists of multiple functions concatenated with “AND” or “OR”. The condition can consist of other mapping constraints like “a is mapped together with b”. This is a derived pattern from M2. Natural Language Requirement: The functions a, b and c shall not be allocated to the same hardware element. Pattern based RSL: function a AND b AND c shall not be mapped to the same target. 6.1.1.5.1 Semantics of Mapping Pattern: In the following we assume that is the set of all functions ∈ and the set of all hardware elements ∈. 138/ 156
The function : allocates a single function on a hardware element written . Using this function the semantics can be defined by the usual semantics of boolean expressions: f shall be mapped to b f1 AND f2 shall be mapped to b ∧ f1 OR f2 shall be mapped to b ∨ f shall be mapped to b1 OR b2 1∨2 f1 AND f2 shall be mapped to b1 OR b2 f1 OR f2 shall be mapped to b1 OR b2 Architecture Modeling ∧ ∨ ∧ ∨ ∨ ∨ The function set expressions can consist of all combinations of conjunctions and disjunctions of functions. These formulas will be applied for the set of hardware elements on the right side of the expression. The semantics related to pattern M2 as follows: f1 shall be mapped together with f2 f1 AND f2 shall be mapped together with f3 ∧ f1 OR f2 shall be mapped to f3 ∨ f1 shall be mapped together with f2 AND f3 ∧ f1 shall be mapped together with f2 OR f3 ∨ f1 AND f2 shall be mapped together with f3 OR f4 ∧ ∨ ∧ The pattern M2 can map multiple boolean combinations of functions together. When combining the left and the right side, the conjunctions are stronger binding than the disjunctions. This type can also be interpreted as a short form of the first type. Any constraint FX shall be mapped together with FY, where FX and FY are arbitrary junctions over functions, can be expressed as FX AND FY shall be mapped to B1 OR ... OR BN. In general, constraints are negated if the not token of the constraint is set: f shall not be mapped to b All constraints can have a precondition which is another constraint. under condition (f2 is mapped to b1) f1 shall be mapped together with f2 → The XOR operator is another short form to make modelling easier. It can be translated into two separate constraint as follows: f1 XOR f2 shall be mapped to b ⇔ f1 AND f2 shall not be mapped together ∧ f1 OR f2 shall be mapped to b 139/ 156
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Architecture Modeling ∗ Andreas B
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Contents 1 Introduction 1 2 Quick-T
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1 Introduction This document propos
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Architecture Modeling allowing to m
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Architecture Modeling creating a vi
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Architecture Modeling the design it
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Architecture Modeling of the logica
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Architecture Modeling realization o
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Architecture Modeling can usually o
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3 The Architecture Meta-Model In Se
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Abstraction-Levels (detail increase
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3.2.2 Functional Perspective Archit
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Architecture Modeling The semantics
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Architecture Modeling expressed by
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Architecture Modeling computing cap
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3.2.5 Geometrical Perspective Archi
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ShapeCompositionOperator intersecti
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Architecture Modeling The constrain
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Architecture Modeling of particular
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Architecture Modeling Shape that de
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Architecture Modeling Conjugation o
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RichComponent Architecture Modeling
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MultiplicityElement +part 0..* Rich
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ComponentC Architecture Modeling pa
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4 Steps in Component-Based Design T
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Architecture Modeling Assume/guaran
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Architecture Modeling When specifyi
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Architecture Modeling next selectio
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Architecture Modeling ports must ha
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established if (and only if): Archi
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Architecture Modeling The component
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Architecture Modeling 4.3.2 Establi
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Architecture Modeling a mapping is
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Architecture Modeling Another impor
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5 Using the Architecture Meta-Model
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Architecture Modeling Design proces
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Architecture Modeling abstraction l
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Pwr1 Pedal_Pos1 Pwr2 Pedal_Pos2 CMD
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Architecture Modeling Figure 5.4: O
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Architecture Modeling Figure 5.9: T
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Page 113 and 114: Architecture Modeling 6.1 Syntax an
Page 115 and 116: 6.1.1.1.1 Attribuute Definit tion a
Page 117 and 118: Constrrain Eventts with Co ondition
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Page 121 and 122: Formalization: whenever StartButton
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Page 125 and 126: 6.1.1.1.1.3 Conditions Conditions c
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Page 133 and 134: If the brake force is above 80% for
Page 135 and 136: Pattern S3: Failure shall not be ca
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Page 139 and 140: Pattern R2: Event occurs each perio
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Page 145 and 146: Examplees of clocks: • Run: {c=0@
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Page 151 and 152: Architecture Modeling Definition 6.
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Page 155 and 156: Architecture Modeling Decomposition
Page 157 and 158: Bibliography [1] ARINC 653 - Avioni
Page 159 and 160: Architecture Modeling [26] Holger G
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Architecture Modeling - SPES 2020

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