Architecture Modeling - SPES 2020
Architecture Modeling - SPES 2020
Architecture Modeling - SPES 2020
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<strong>Architecture</strong> <strong>Modeling</strong><br />
a mapping is similar to a component. It has interfaces consisting of ports, and it has internal<br />
behavior defined in terms of an HRC state machine. Its interfaces are however not used for<br />
interaction with other components but to relate different models. As Figure 4.10 shows, a mapping<br />
connects (arbitrary) ports of two different models of a design. Mappings are asymmetric<br />
in that the roles of connected model artifacts are different. A mapping can be considered as an<br />
observer of one of the participating models. In Figure 4.10 for example, the depicted mapping<br />
“observes” the behavior of component S of the right hand model. Due to its internal behavior,<br />
a mapping provides a well defined (possibly modified) view to the behavior of the “observed”<br />
model. More important, the observer approach gives means to the fact, that models of a design<br />
are closely related to each other. Model artifacts within a perspective at a certain abstraction<br />
level are allocated to artifacts of other perspectives, and artifacts at a lower level are considered<br />
to realize those of a higher abstraction level. In this sense, a mapping provides the foundation<br />
to reason about satisfaction of an observing model by another (observed) model.<br />
Logical Perspective<br />
temp occurs each<br />
50ms<br />
temp<br />
Delay between temp and control within<br />
[20ms,25ms]<br />
AirTempSystem<br />
control<br />
Mapping<br />
Technical Perspective<br />
tempVal<br />
temp<br />
temp<br />
Data<br />
control<br />
Var1<br />
ECU<br />
Capture<br />
Task<br />
Figure 4.10: Mapping Example<br />
Scheduler<br />
airTemp<br />
CtrlTask<br />
Technically, a mapping can be used to “replace” components within the observing model, as<br />
depicted in Figure 4.11. While replacing, the mapping gets associated with the set of contracts<br />
that have been associated to the replaced components. This gives means to the proof obligation<br />
corresponding to the question whether the observed model satisfies the contracts defined for the<br />
observing model. In fact, the situation is very similar to those of virtual integration testing. If<br />
the resulting system, containing the mapping and the observed model, is considered as a single<br />
component as shown in Figure 4.11, the same proof obligations apply as for VIT. However,<br />
refinement has to be shown not for the composition of all contracts in the observed model, but<br />
only for the composition of those contracts that are associated to components having links to the<br />
mapping. The result is that, whenever the contracts of the components of the observed model<br />
are satisfied, then the contracts of the observing models are also satisfied with respect to the<br />
internal behavior of the mapping.<br />
Mappings thus provide well-defined interfaces between artifacts of models within different<br />
perspectives and abstraction levels. However, the corresponding proof obligations are valid only<br />
with respect to the behavior of the mapping. Mapping can for example be used to perform interface<br />
refinement. The upper part of Figure 4.12 shows a component with an outport providing<br />
some integer valued data. At the next lower abstraction level, the same component has a refined<br />
port providing 3-Bit digital data. The mapping shown in the figure “converts” the 3-Bit values<br />
of the refined component into (more abstract) integer values. In this example, the internal be-<br />
Var2<br />
tempSel<br />
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