Architecture Modeling - SPES 2020

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Architecture Modeling Figure 5.20: Unit Level – Allocation from Logical to Technical Perspective ECU1 has two contracts specifying the local deadlines for the execution of the two tasks ECU1Task1 and ECU1Task2. To choose the correct deadlines here, the allocation of logical components to tasks of the technical perspective is necessary. The allocation is depicted in Figure 5.20 while we use here an abbreviatory representation of the mapping of a single port to another single port. A dotted arrow from a port a of a logical component (depicted on the left side) to a port b of a technical component (depicted on the right side) means a mapping of port a to port b. The dottet arrow from one component to another component annotated with an > label indicates this mapping as an allocation. For ECU1, the relevant allocation decisions are the mapping of Monitor1 to ECU1Task2 and the mapping of Command2 to ECU1Task1. This leads to the contracts in Figure 5.19 specifying the same deadlines as for the mapped logical components i.e. a deadline of 1200 microseconds for the execution (inclusive scheduling) of ECU1Task2 (delay from input signal inA.P TecBusA to outA.P TecA) and a deadline of 1400 microseconds for ECU1Task1 (delay from input signal inB.P TecB to outB.P TecBusB). The structure of the component ECU2 is almost similar to ECU1 and thus not depicted here. The mapping to the tasks of ECU2 is also shown in the allocation in Figure 5.20. Communication components such as Com1ToMon1 and Com2ToMon2 are mapped implicitly by the task mapping. The interna of the bus component CANBus are shown in Figure 5.21. It consists of a scheduler component (depicted in blue) that schedules two slots (depicted in green). Each slot is then linked to a frame-triggering component that sends and receives the frames. Again, we have two contracts specifying how long a communication may take which is the identical deadline of 400 microseconds as for the logical communication components. Scheduling Analysis with Orca Next, we want to show exemplarily how real-time contracts may be checked using a scheduling analysis tool like Orca. The first step is the translation of the model into the Orca data model. The result of this 90/ 156
Architecture Modeling Figure 5.21: Technical Perspective – Unit Level – Bus Figure 5.22: Orca Model of Unit Level translation is depicted in Figure 5.22. On the left side, a task network is shown consisting of triggers, tasks, signals, messages and deadlines while at the right edge of the figure the set 91/ 156
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Architecture Modeling ∗ Andreas B
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Contents 1 Introduction 1 2 Quick-T
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1 Introduction This document propos
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Architecture Modeling allowing to m
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Architecture Modeling creating a vi
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Architecture Modeling the design it
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Architecture Modeling of the logica
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Architecture Modeling realization o
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Architecture Modeling can usually o
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3 The Architecture Meta-Model In Se
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Abstraction-Levels (detail increase
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3.2.2 Functional Perspective Archit
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Architecture Modeling The semantics
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Architecture Modeling expressed by
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Architecture Modeling computing cap
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3.2.5 Geometrical Perspective Archi
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ShapeCompositionOperator intersecti
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Architecture Modeling The constrain
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Architecture Modeling Traces accord
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Architecture Modeling Definition 6.
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Architecture Modeling the one given
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Architecture Modeling Decomposition
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Bibliography [1] ARINC 653 - Avioni
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Architecture Modeling [26] Holger G
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