X9DR3_i-LN4F+ 1.1.indb - Supermicro
X9DR3_i-LN4F+ 1.1.indb - Supermicro
X9DR3_i-LN4F+ 1.1.indb - Supermicro
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1<br />
1<br />
Chapter 2: Installation<br />
Fan Headers<br />
This motherboard has eight system/CPU<br />
fan headers (Fan 1~Fan 6, Fan A, Fan<br />
B) on the motherboard. All these 4-pin<br />
fans headers are backward compatible<br />
with the traditional 3-pin fans. However,<br />
fan speed control is available for 4-pin<br />
fans only. The fan speeds are controlled<br />
by Firmware Thermal Management via<br />
IPMI 2.0. See the table on the right for<br />
pin definitions.<br />
Pin#<br />
Fan Header<br />
Pin Definitions<br />
Definition<br />
1 Ground<br />
2 +12V<br />
3 Tachometer<br />
4 Firmware Thermal<br />
Management<br />
Chassis Intrusion<br />
A Chassis Intrusion header is located<br />
at JL1 on the motherboard. Attach an<br />
appropriate cable from the chassis to<br />
inform you of a chassis intrusion when<br />
the chassis is opened.<br />
Pin#<br />
Chassis Intrusion<br />
Pin Definitions<br />
Definition<br />
1 Intrusion Input<br />
2 Ground<br />
LE2<br />
SW1<br />
UID<br />
VGA<br />
LAN2/4<br />
F<br />
LAN1/3 USB 2/3 USB 0/1 COM1<br />
FAN6<br />
E<br />
IPMB<br />
JPME2<br />
JPG1<br />
JTPM1<br />
J21<br />
JL1<br />
J17<br />
JI2C2<br />
JI2C1<br />
USB6/7<br />
JBMC1<br />
JSTBY1<br />
USB4/5<br />
JWD1<br />
I-SATA4<br />
JPME1<br />
I-SATA2<br />
I-SATA0<br />
COM2<br />
USB9<br />
J18<br />
I<br />
I-SATA5<br />
I-SATA3<br />
I-SATA1<br />
JSD1<br />
LEM1<br />
CPU1 Slot1 PCI-E 3.0 x16<br />
SAS<br />
CTRL<br />
XDP-PCH<br />
JRK1<br />
BIOS<br />
JBT1<br />
SAS4~7<br />
BMC<br />
CTRL<br />
CPU1 Slot2 PCI-E 3.0 x4 (in X8 slot)<br />
JWP1<br />
PCH<br />
SAS0~3<br />
FANB<br />
CPU1 Slot3 PCI-E 3.0 x16<br />
JPB1<br />
BIOS BOX<br />
XDP-CPU<br />
FANA<br />
CPU2 Slot4 PCI-E 3.0 x16<br />
JP7<br />
JP6<br />
JOH1<br />
JD1<br />
LAN<br />
CTRL<br />
SP1<br />
JF2<br />
JBAT1<br />
FAN4<br />
CPU2 Slot5 PCI-E 3.0 x16<br />
JPL1<br />
CPU2 Slot6 PCI-E 3.0 x8<br />
Alaways populate DIMMx1 first<br />
P1 DIMMD3<br />
P1 DIMMD2<br />
P1 DIMMD1<br />
P1 DIMMC3<br />
P1 DIMMC2<br />
P1 DIMMC1<br />
FAN3<br />
JF1<br />
P2 DIMMF3<br />
P2 DIMMF2<br />
P2 DIMMF1<br />
P2 DIMME3<br />
P2 DIMME2<br />
P2 DIMME1<br />
Alaways populate DIMMx1 first<br />
LE1<br />
IPMI_LAN<br />
<strong>X9DR3</strong>-<strong>LN4F+</strong>/X9DRi-<strong>LN4F+</strong><br />
Rev. 1.10<br />
CPU1<br />
CPU2<br />
P1 DIMMA1<br />
P1 DIMMA2<br />
P1 DIMMA3<br />
P1 DIMMB1<br />
P1 DIMMB2<br />
P1 DIMMB3<br />
FAN2<br />
P2 DIMMG1<br />
P2 DIMMG2<br />
P2 DIMMG3<br />
P2 DIMMH1<br />
P2 DIMMH2<br />
P2 DIMMH3<br />
JPW3 JPW2 JPW1<br />
FAN1<br />
FAN5<br />
PHY<br />
JPI2C1<br />
A. Fan 1<br />
B. Fan 2<br />
C. Fan 3<br />
D. Fan 4<br />
E. Fan 5<br />
F. Fan 6<br />
G. Fan A<br />
H. Fan B<br />
I. Chassis Intrusion<br />
H<br />
G<br />
D<br />
C<br />
B<br />
A<br />
2-29
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