X9DR3_i-LN4F+ 1.1.indb - Supermicro
X9DR3_i-LN4F+ 1.1.indb - Supermicro
X9DR3_i-LN4F+ 1.1.indb - Supermicro
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<strong>X9DR3</strong>-<strong>LN4F+</strong>/X9DRi-<strong>LN4F+</strong> Motherboard User’s Manual<br />
Intel I/OAT<br />
The Intel I/OAT (I/O Acceleration Technology) significantly reduces CPU overhead<br />
by leveraging CPU architectural improvements, freeing the system resource<br />
for other tasks. The options are Disabled and Enabled.<br />
DCA Support<br />
Select Enabled to use Intel's DCA (Direct Cache Access) Technology to improve<br />
data transfer efficiency. The options are Enabled and Disabled.<br />
MMCFG (Memory Mapped Configuration) BASE<br />
This item allows the user to set the default PCI MMIO base address. The lower<br />
the MMIO base address is, the less available the system memory is in a 32-bit<br />
OS. The default setting is [0x80000000].<br />
IIO 1 PCIe Port Bifurcation Control<br />
This submenu configures the following IO PCIe Port Bifurcation Control settings<br />
for IIO 1 PCIe ports to determine how the available PCI-Express lanes to be<br />
distributed between the PCI-Exp. Root Ports.<br />
Uplink Link Speed<br />
This feature allows the user to select target link speed. The options are Gen1<br />
(Generation 1), Gen2 and Gen3.<br />
CPU1 Slot2 PCI-E 3.0 x4 Link Speed<br />
This feature allows the user to set the PCI-Exp bus speed for the slot specified<br />
above. The options are Gen1 (Generation 1), Gen2 and Gen3.<br />
CPU1 Slot3 PCI-E 3.0 x16 Link Speed<br />
This feature allows the user to set the PCI-Exp bus speed for the slot specified<br />
above. The options are Gen1 (Generation 1), Gen2 and Gen3.<br />
CPU1 Slot1 PCI-E 3.0 x16 Link Speed<br />
This feature allows the user to set the PCI-Exp bus speed for the slot specified<br />
above. The options are Gen1 (Generation 1), Gen2 and Gen3.<br />
IIO 2 PCIe Port Bifurcation Control<br />
This submenu configures the following IO PCIe Port Bifurcation Control settings<br />
for IIO 2 PCIe ports to determine how the available PCI-Express lanes to be<br />
distributed between the PCI-Exp. Root Ports.<br />
CPU2 Slot6 PCI-E 3.0 x8 Link Speed<br />
This feature allows the user to set the PCI-Exp bus speed for the slot specified<br />
above. The options are Gen1 (Generation 1), Gen2 and Gen3.<br />
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