Hardware Interface Description - KORE Telematics
Hardware Interface Description - KORE Telematics
Hardware Interface Description - KORE Telematics
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XT55/56 <strong>Hardware</strong> <strong>Interface</strong> <strong>Description</strong><br />
Confidential / Released<br />
s<br />
Note:<br />
Before starting the data transfer the clock GSM_SCLK should be available for at<br />
least three cycles.<br />
After the transfer of the LSB0 the clock GSM_SCLK should be still available for at<br />
least three cycles.<br />
minimum possible distance = 25 bit periods<br />
GSM_SLCK<br />
(input)<br />
Internal<br />
signal<br />
GSM_RFSDAI<br />
(input)<br />
= T<br />
T = 100ns to 5,000 ns<br />
= T = T<br />
GSM_RXDDAI<br />
(input)<br />
MSB<br />
15<br />
Bit<br />
14<br />
Bit<br />
13<br />
Bit<br />
12<br />
Bit<br />
11<br />
Bit<br />
10<br />
Bit<br />
9<br />
Bit<br />
8<br />
Bit<br />
7<br />
Bit<br />
6<br />
Bit<br />
5<br />
Bit<br />
4<br />
Bit<br />
3<br />
Bit<br />
2<br />
Bit<br />
1<br />
LSB<br />
0<br />
MSB<br />
15<br />
Flag<br />
< 1.5 SCLK<br />
cycles<br />
< 1 DSP cycle<br />
automatic reset after<br />
reading to DAIRD<br />
interrupt on INTO<br />
after 3 DSP cycles<br />
Figure 17: DAI timing on transmit path<br />
GSM_SLCK<br />
(input)<br />
Internal<br />
signal<br />
GSM_TFSDAI<br />
(output)<br />
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