Hardware Interface Description - KORE Telematics

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XT55/56 Hardware Interface Description Confidential / Released s 4.6 Serial interfaces of the XT55/56 GPS part The GPS part of the XT55/56 module offers two serial interfaces: SD1 • 2-wire serial interface • Includes the SDI1 (receive) and SDO1 (transmit) lines • Supported baud rate: 9600…115200 bps. See also [1] for details on the used GPS protocol. SD2 • 2-wire serial interface • Includes the SDI2 (receive) and SDO2 (transmit) lines. It is intended for communication with the GSM/ GPRS part of the XT55/56 module. See Figure 1 for details. • Supported baud rate: 9600…115200 bps. See also [1] for details on the used GPS protocol. SD1 and SD2 • Both interfaces are configured for 8 data bits, no parity and 1 stop bit • For more detailed characteristics see [1] 4.7 GPS control signals GPS_M-RST: This pin provides an active-low reset input to the board. It causes the board to reset and start searching for satellites. Reset is an optional input and, if not utilized, it may be left open. GPS_BOOTSEL: Set this pin to high for reprogramming the flash of the XT55/56 GPS part (for instance updating to a new XT55/56 GPS firmware). GPS_RFPC0, GPS_RFPC1 (including pull-up resistors): These pins are input pins for Trickle-Power mode control. To use the Trickle- Power mode function connect the RFPC0 and RFPC1 as shown in Figure 58. The pull-up resistors ensure the correct voltage level during start-up and reset procedure of the GPS base band processor. GPS_GPIO8, GPS_GPIO4: These pins are control outputs for the Trickle-Power mode. GPS_GPIO8 must be connected to GPS_RFPC0 and GPS_GPIO4 to GPS_RFPC1. GPS_GPIO8, GPS_GPIO4 can also be used to control a LED. A possible circuit is shown in Figure 29. If the LED lights permanently the GPS receiver is searching for satellites. If the GPS receiver is in Trickle-Power mode, the LED flashes in rhythm, i.e. the GPS receiver receives valid position data. Timing differs between GPS_GPIO4 and GPS_GPIO8. Note: If Trickle power is switched off the LED lights permanently. XT55/56_hd_v02.06a Page 76 of 125 17.12.2004
XT55/56 Hardware Interface Description Confidential / Released s Vcc = 3.3 V DC GPS_RFPC0, GPS_RFPC1 330 Ω BC817 47 k Ω GND Figure 29: Example of LED circuit 4.8 Receiver architecture The XT55/56 GPS receiver is a product that features the SiRFstarII-Low Power chipset. It is a complete 12 channel, WAAS-enabled GPS receiver which provides a vastly superior position accuracy performance. The SiRFstarII architecture builds on the high-performance SiRFstarI core, adding an acquisition accelerator, differential GPS processor, multipath mitigation hardware and satellite-tracking engine. The XT55/56 GPS receiver delivers major advancements in GPS performance, accuracy, integration, computing power and flexibility. Antenna input BOOTSELECT RECEIVER ARCHITECTURE XTAL LNA RF Filter GRF2i/LP RF Front-End GPS-Data AGC Clock RTC GSP2e/LP Signal Processor 2 x PWRCTL (RFPC) GPS_SDI 1 GPS_SDO 1 GPS_SDO 2 GPS_SDI 2 12 x GPS_GPIO TCXO Data Bus GPS_VCC_RF Address Bus GPS_VANT GPS_VCC (+3.3 V DC) Reset IC GPS_M-RST FLASH 1MByte Figure 30: Receiver architecture of the GPS receiver XT55/56_hd_v02.06a Page 77 of 125 17.12.2004
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Hardware Interface Description - KORE Telematics

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