ATMega chip full datasheet - UCSD Department of Physics

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ATmega48A/PA/88A/PA/168A/PA/328/Psymmetry around BOTTOM the OCnx value at MAX must correspond to the result of an upcountingCompare Match.• The timer starts counting from a value higher than the one in OCRnx, and for that reasonmisses the Compare Match and hence the OCnx change that would have happened on theway up.15.8 Timer/Counter Timing DiagramsThe Timer/Counter is a synchronous design and the timer clock (clk T0 ) is therefore shown as aclock enable signal in the following figures. The figures include information on when interruptflags are set. Figure 15-8 contains timing data for basic Timer/Counter operation. The figureshows the count sequence close to the MAX value in all modes other than phase correct PWMmode.Figure 15-8.Timer/Counter Timing Diagram, no Prescalingclk I/Oclk Tn(clk I/O/1)TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1TOVnFigure 15-9 shows the same timing data, but with the prescaler enabled.Figure 15-9. Timer/Counter Timing Diagram, with Prescaler (f clk_I/O /8)clk I/Oclk Tn(clk I/O/8)TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1TOVnFigure 15-10 shows the setting of OCF0B in all modes and OCF0A in all modes except CTCmode and PWM mode, where OCR0A is TOP.8271D–AVR–05/11106
ATmega48A/PA/88A/PA/168A/PA/328/PFigure 15-10. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (f clk_I/O /8)clk I/Oclk Tn(clk I/O/8)TCNTnOCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2OCRnxOCRnx ValueOCFnxFigure 15-11 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fastPWM mode where OCR0A is TOP.Figure 15-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler(f clk_I/O /8)clk I/Oclk Tn(clk I/O/8)TCNTn(CTC)TOP - 1 TOP BOTTOM BOTTOM + 1OCRnxTOPOCFnx8271D–AVR–05/11107
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Atmel Corporation2325 Orchard Parkw
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ATMega chip full datasheet - UCSD Department of Physics

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