ATMega chip full datasheet - UCSD Department of Physics

ATmega48A/PA/88A/PA/168A/PA/328/PFigure 22-12. Formats and States in the Master Transmitter ModeMTSuccessfulltransmissionto a slavereceiverS SLA W A DATA A P$08 $18 $28Next transferstarted with arepeated startconditionRSSLA W$10Not acknowledgereceived after theslave addressAPR$20Not acknowledgereceived after a databyteAPMR$30Arbitration lost in slaveaddress or data byteA or AOther mastercontinuesA or AOther mastercontinues$38$38Arbitration lost andaddressed as slaveAOther mastercontinues$68$78 $B0To correspondingstates in slave modeFrom master to slaveDATAAAny number of data bytesand their associated acknowledge bitsFrom slave to masternThis number (contained in TWSR) correspondsto a defined state of the 2-Wire Serial Bus. Theprescaler bits are zero or masked to zero22.7.2 Master Receiver ModeIn the Master Receiver mode, a number of data bytes are received from a Slave Transmitter(Slave see Figure 22-13). In order to enter a Master mode, a START condition must be transmitted.The format of the following address packet determines whether Master Transmitter orMaster Receiver mode is to be entered. If SLA+W is transmitted, MT mode is entered, if SLA+Ris transmitted, MR mode is entered. All the status codes mentioned in this section assume thatthe prescaler bits are zero or are masked to zero.8271D–AVR–05/11232