ATMega chip full datasheet - UCSD Department of Physics

ATmega48A/PA/88A/PA/168A/PA/328/PIn Free Running mode, a new conversion will be started immediately after the conversion completes,while ADSC remains high. For a summary of conversion times, see Table 24-1 on page257.Figure 24-4.ADC Timing Diagram, First Conversion (Single Conversion Mode)First ConversionNextConversionCycle Number1 2 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 23ADC ClockADENADSCADIFADCHADCLSign and MSB of ResultLSB of ResultMUX and REFSUpdateSample & HoldConversionCompleteMUX and REFSUpdateFigure 24-5.ADC Timing Diagram, Single ConversionOne ConversionNext ConversionCycle Number 1 2 3 4 5 6 7 8 9 10 11 12 131 23ADC ClockADSCADIFADCHSign and MSB of ResultADCLLSB of ResultSample & HoldMUX and REFSUpdateConversionCompleteMUX and REFSUpdateFigure 24-6.ADC Timing Diagram, Auto Triggered ConversionOne ConversionNext ConversionCycle Number 1 2 3 4 5 6 7 8 9 10 11 12 131 2ADC ClockTriggerSourceADATEADIFADCHSign and MSB of ResultADCLLSB of ResultPrescalerResetMUX and REFSUpdateSample &HoldConversionCompletePrescalerReset8271D–AVR–05/11256